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| author | 2018-04-06 14:26:03 +0000 | |
|---|---|---|
| committer | 2018-04-06 14:26:03 +0000 | |
| commit | bdabc2f19ffb9e20600dad6e8a300842a7bda50e (patch) | |
| tree | c50e7b2e5449b074651bb82a58517a8ebc4a8cf7 /gnu/llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp | |
| parent | Print a 'p' flag for file descriptors that were opened after pledge(2). (diff) | |
| download | wireguard-openbsd-bdabc2f19ffb9e20600dad6e8a300842a7bda50e.tar.xz wireguard-openbsd-bdabc2f19ffb9e20600dad6e8a300842a7bda50e.zip | |
Import LLVM 6.0.1 release including clang, lld and lldb.
"where is the kaboom?" deraadt@
Diffstat (limited to 'gnu/llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp')
| -rw-r--r-- | gnu/llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/gnu/llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp b/gnu/llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp new file mode 100644 index 00000000000..534f78c6d4d --- /dev/null +++ b/gnu/llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp @@ -0,0 +1,47 @@ +//===-- ARMBaseInfo.cpp - ARM Base encoding information------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides basic encoding and assembly information for ARM. +// +//===----------------------------------------------------------------------===// +#include "ARMBaseInfo.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/SmallVector.h" + +using namespace llvm; +namespace llvm { +namespace ARMSysReg { + +// lookup system register using 12-bit SYSm value. +// Note: the search is uniqued using M1 mask +const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm) { + return lookupMClassSysRegByM1Encoding12(SYSm); +} + +// returns APSR with _<bits> qualifier. +// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier +const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm) { + return lookupMClassSysRegByM2M3Encoding8((1<<9)|(SYSm & 0xFF)); +} + +// lookup system registers using 8-bit SYSm value +const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm) { + return ARMSysReg::lookupMClassSysRegByM2M3Encoding8((1<<8)|(SYSm & 0xFF)); +} + +#define GET_MCLASSSYSREG_IMPL +#include "ARMGenSystemRegister.inc" + +} // end namespace ARMSysReg + +namespace ARMBankedReg { +#define GET_BANKEDREG_IMPL +#include "ARMGenSystemRegister.inc" +} // end namespce ARMSysReg +} // end namespace llvm |
