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| author | 2017-01-24 08:32:59 +0000 | |
|---|---|---|
| committer | 2017-01-24 08:32:59 +0000 | |
| commit | 53d771aafdbe5b919f264f53cba3788e2c4cffd2 (patch) | |
| tree | 7eca39498be0ff1e3a6daf583cd9ca5886bb2636 /gnu/llvm/lib/Target/AVR/AVRTargetMachine.cpp | |
| parent | In preparation of compiling our kernels with -ffreestanding, explicitly map (diff) | |
| download | wireguard-openbsd-53d771aafdbe5b919f264f53cba3788e2c4cffd2.tar.xz wireguard-openbsd-53d771aafdbe5b919f264f53cba3788e2c4cffd2.zip | |
Import LLVM 4.0.0 rc1 including clang and lld to help the current
development effort on OpenBSD/arm64.
Diffstat (limited to 'gnu/llvm/lib/Target/AVR/AVRTargetMachine.cpp')
| -rw-r--r-- | gnu/llvm/lib/Target/AVR/AVRTargetMachine.cpp | 25 |
1 files changed, 19 insertions, 6 deletions
diff --git a/gnu/llvm/lib/Target/AVR/AVRTargetMachine.cpp b/gnu/llvm/lib/Target/AVR/AVRTargetMachine.cpp index 508723e91c6..fb3262916b4 100644 --- a/gnu/llvm/lib/Target/AVR/AVRTargetMachine.cpp +++ b/gnu/llvm/lib/Target/AVR/AVRTargetMachine.cpp @@ -25,6 +25,8 @@ namespace llvm { +static const char *AVRDataLayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-n8"; + /// Processes a CPU name. static StringRef getCPU(StringRef CPU) { if (CPU.empty() || CPU == "generic") { @@ -44,7 +46,7 @@ AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT, Optional<Reloc::Model> RM, CodeModel::Model CM, CodeGenOpt::Level OL) : LLVMTargetMachine( - T, "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-i64:8:8-f32:8:8-f64:8:8-n8", TT, + T, AVRDataLayout, TT, getCPU(CPU), FS, Options, getEffectiveRelocModel(RM), CM, OL), SubTarget(TT, getCPU(CPU), FS, *this) { this->TLOF = make_unique<AVRTargetObjectFile>(); @@ -65,7 +67,6 @@ public: bool addInstSelector() override; void addPreSched2() override; void addPreRegAlloc() override; - void addPreEmitPass() override; }; } // namespace @@ -75,7 +76,12 @@ TargetPassConfig *AVRTargetMachine::createPassConfig(PassManagerBase &PM) { extern "C" void LLVMInitializeAVRTarget() { // Register the target. - RegisterTargetMachine<AVRTargetMachine> X(TheAVRTarget); + RegisterTargetMachine<AVRTargetMachine> X(getTheAVRTarget()); + + auto &PR = *PassRegistry::getPassRegistry(); + initializeAVRExpandPseudoPass(PR); + initializeAVRInstrumentFunctionsPass(PR); + initializeAVRRelaxMemPass(PR); } const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const { @@ -91,15 +97,22 @@ const AVRSubtarget *AVRTargetMachine::getSubtargetImpl(const Function &) const { //===----------------------------------------------------------------------===// bool AVRPassConfig::addInstSelector() { + // Install an instruction selector. + addPass(createAVRISelDag(getAVRTargetMachine(), getOptLevel())); + // Create the frame analyzer pass used by the PEI pass. + addPass(createAVRFrameAnalyzerPass()); + return false; } void AVRPassConfig::addPreRegAlloc() { + // Create the dynalloc SP save/restore pass to handle variable sized allocas. + addPass(createAVRDynAllocaSRPass()); } -void AVRPassConfig::addPreSched2() { } - -void AVRPassConfig::addPreEmitPass() { +void AVRPassConfig::addPreSched2() { + addPass(createAVRRelaxMemPass()); + addPass(createAVRExpandPseudoPass()); } } // end of namespace llvm |
