Add retguard for octeon/mips64.

For this architecture we use separate retguard prologue and epilogue code
for static or PIC code. In the PIC case we use some additional code before
the retguard epilogue to recover the function start address and the GOT
pointer in order to get the per-function random cookie. Much thanks to
visa@ for suggestions and advice making it all work.

ok deraadt@ visa@

1 files changed, 9 insertions, 0 deletions

diff --git a/gnu/llvm/lib/Target/Mips/MipsFrameLowering.cpp b/gnu/llvm/lib/Target/Mips/MipsFrameLowering.cpp
index 27a85970da6..54cac00577f 100644
--- a/gnu/llvm/lib/Target/Mips/MipsFrameLowering.cpp
+++ b/gnu/llvm/lib/Target/Mips/MipsFrameLowering.cpp
@@ -15,6 +15,7 @@
 #include "MCTargetDesc/MipsBaseInfo.h"
 #include "MipsInstrInfo.h"
 #include "MipsMachineFunction.h"
+#include "MipsReturnProtectorLowering.h"
 #include "MipsTargetMachine.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
@@ -123,6 +124,10 @@ uint64_t MipsFrameLowering::estimateStackSize(const MachineFunction &MF) const {
     if (MFI.getObjectOffset(I) > 0)
       Size += MFI.getObjectSize(I);
 
+  // Account for saving return protector register
+  if (MFI.getReturnProtectorNeeded())
+    Size += TRI.getSpillSize(*TRI.getMinimalPhysRegClass(Mips::T9_64));
+
   // Conservatively assume all callee-saved registers will be saved.
   for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) {
     unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R));
@@ -150,3 +155,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
 
   return MBB.erase(I);
 }
+
+const ReturnProtectorLowering *MipsFrameLowering::getReturnProtector() const {
+  return &RPL;
+}