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| author |   patrick <patrick@openbsd.org> | 2017-01-14 19:55:43 +0000 |
|---|---|---|
| committer | patrick <patrick@openbsd.org> | 2017-01-14 19:55:43 +0000 |
| commit | bd3306aecb3a15e8967143b8cdbbccf2b1b19b74 (patch) | |
| tree | 309a8132b44564b9e634c0da6815187ce8eab27c /gnu/llvm/lib/Target/Mips/MipsSubtarget.cpp | |
| parent | killp -a should not kill the window if only one pane. (diff) | |
| download | wireguard-openbsd-bd3306aecb3a15e8967143b8cdbbccf2b1b19b74.tar.xz wireguard-openbsd-bd3306aecb3a15e8967143b8cdbbccf2b1b19b74.zip | |
Import LLVM 3.9.1 including clang and lld.
Diffstat (limited to 'gnu/llvm/lib/Target/Mips/MipsSubtarget.cpp')
| -rw-r--r-- | gnu/llvm/lib/Target/Mips/MipsSubtarget.cpp | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/gnu/llvm/lib/Target/Mips/MipsSubtarget.cpp b/gnu/llvm/lib/Target/Mips/MipsSubtarget.cpp index 8a18b517d16..3e7570ff46e 100644 --- a/gnu/llvm/lib/Target/Mips/MipsSubtarget.cpp +++ b/gnu/llvm/lib/Target/Mips/MipsSubtarget.cpp @@ -90,7 +90,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU, report_fatal_error("Code generation for MIPS-V is not implemented", false); // Check if Architecture and ABI are compatible. - assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) || + assert(((!isGP64bit() && isABI_O32()) || (isGP64bit() && (isABI_N32() || isABI_N64()))) && "Invalid Arch & ABI pair."); @@ -114,7 +114,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU, report_fatal_error(ISA + " is not compatible with the DSP ASE", false); } - if (NoABICalls && TM.getRelocationModel() == Reloc::PIC_) + if (NoABICalls && TM.isPositionIndependent()) report_fatal_error("position-independent code requires '-mabicalls'"); // Set UseSmallSection. @@ -126,6 +126,10 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU, } } +bool MipsSubtarget::isPositionIndependent() const { + return TM.isPositionIndependent(); +} + /// This overrides the PostRAScheduler bit in the SchedModel for any CPU. bool MipsSubtarget::enablePostRAScheduler() const { return true; } @@ -164,7 +168,6 @@ Reloc::Model MipsSubtarget::getRelocationModel() const { return TM.getRelocationModel(); } -bool MipsSubtarget::isABI_EABI() const { return getABI().IsEABI(); } bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); } bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); } bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); } |