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authorpatrick <patrick@openbsd.org>2018-04-06 14:26:03 +0000
committerpatrick <patrick@openbsd.org>2018-04-06 14:26:03 +0000
commitbdabc2f19ffb9e20600dad6e8a300842a7bda50e (patch)
treec50e7b2e5449b074651bb82a58517a8ebc4a8cf7 /gnu/llvm/lib/Target/X86/X86MacroFusion.cpp
parentPrint a 'p' flag for file descriptors that were opened after pledge(2). (diff)
downloadwireguard-openbsd-bdabc2f19ffb9e20600dad6e8a300842a7bda50e.tar.xz
wireguard-openbsd-bdabc2f19ffb9e20600dad6e8a300842a7bda50e.zip
Import LLVM 6.0.1 release including clang, lld and lldb.
"where is the kaboom?" deraadt@
Diffstat (limited to 'gnu/llvm/lib/Target/X86/X86MacroFusion.cpp')
-rw-r--r--gnu/llvm/lib/Target/X86/X86MacroFusion.cpp16
1 files changed, 7 insertions, 9 deletions
diff --git a/gnu/llvm/lib/Target/X86/X86MacroFusion.cpp b/gnu/llvm/lib/Target/X86/X86MacroFusion.cpp
index 8fdf1061705..67d95c2233d 100644
--- a/gnu/llvm/lib/Target/X86/X86MacroFusion.cpp
+++ b/gnu/llvm/lib/Target/X86/X86MacroFusion.cpp
@@ -14,8 +14,8 @@
#include "X86MacroFusion.h"
#include "X86Subtarget.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/CodeGen/MacroFusion.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
using namespace llvm;
@@ -27,10 +27,8 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
const MachineInstr *FirstMI,
const MachineInstr &SecondMI) {
const X86Subtarget &ST = static_cast<const X86Subtarget&>(TSI);
- // Check if this processor supports macro-fusion. Since this is a minor
- // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
- // proxy for SandyBridge+.
- if (!ST.hasAVX())
+ // Check if this processor supports macro-fusion.
+ if (!ST.hasMacroFusion())
return false;
enum {
@@ -84,10 +82,10 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
case X86::TEST32i32:
case X86::TEST64i32:
case X86::TEST64ri32:
- case X86::TEST8rm:
- case X86::TEST16rm:
- case X86::TEST32rm:
- case X86::TEST64rm:
+ case X86::TEST8mr:
+ case X86::TEST16mr:
+ case X86::TEST32mr:
+ case X86::TEST64mr:
case X86::TEST8ri_NOREX:
case X86::AND16i16:
case X86::AND16ri: