summaryrefslogtreecommitdiffstats
path: root/gnu/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
diff options
context:
space:
mode:
authorpatrick <patrick@openbsd.org>2017-10-04 20:27:34 +0000
committerpatrick <patrick@openbsd.org>2017-10-04 20:27:34 +0000
commit31eb748944903b7f4f38afda9851951ca9dfc1ae (patch)
tree9b95b6ea45d0874d75eb05b90c0840e191416439 /gnu/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
parentDon't try to handle IPv4-compatible IPv6 addresses (diff)
downloadwireguard-openbsd-31eb748944903b7f4f38afda9851951ca9dfc1ae.tar.xz
wireguard-openbsd-31eb748944903b7f4f38afda9851951ca9dfc1ae.zip
Import LLVM 5.0.0 release including clang, lld and lldb.
Diffstat (limited to 'gnu/llvm/lib/Target/XCore/XCoreTargetMachine.cpp')
-rw-r--r--gnu/llvm/lib/Target/XCore/XCoreTargetMachine.cpp24
1 files changed, 15 insertions, 9 deletions
diff --git a/gnu/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/gnu/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
index bf3138f2164..cb23399995d 100644
--- a/gnu/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
+++ b/gnu/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
@@ -11,14 +11,18 @@
//===----------------------------------------------------------------------===//
#include "XCoreTargetMachine.h"
+#include "MCTargetDesc/XCoreMCTargetDesc.h"
+#include "XCore.h"
#include "XCoreTargetObjectFile.h"
#include "XCoreTargetTransformInfo.h"
-#include "XCore.h"
+#include "llvm/ADT/Optional.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
-#include "llvm/IR/Module.h"
-#include "llvm/IR/LegacyPassManager.h"
+#include "llvm/Support/CodeGen.h"
#include "llvm/Support/TargetRegistry.h"
+
using namespace llvm;
static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
@@ -38,18 +42,19 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT,
: LLVMTargetMachine(
T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32",
TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM, OL),
- TLOF(make_unique<XCoreTargetObjectFile>()),
+ TLOF(llvm::make_unique<XCoreTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this) {
initAsmInfo();
}
-XCoreTargetMachine::~XCoreTargetMachine() {}
+XCoreTargetMachine::~XCoreTargetMachine() = default;
namespace {
+
/// XCore Code Generator Pass Configuration Options.
class XCorePassConfig : public TargetPassConfig {
public:
- XCorePassConfig(XCoreTargetMachine *TM, PassManagerBase &PM)
+ XCorePassConfig(XCoreTargetMachine &TM, PassManagerBase &PM)
: TargetPassConfig(TM, PM) {}
XCoreTargetMachine &getXCoreTargetMachine() const {
@@ -61,14 +66,15 @@ public:
bool addInstSelector() override;
void addPreEmitPass() override;
};
-} // namespace
+
+} // end anonymous namespace
TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) {
- return new XCorePassConfig(this, PM);
+ return new XCorePassConfig(*this, PM);
}
void XCorePassConfig::addIRPasses() {
- addPass(createAtomicExpandPass(&getXCoreTargetMachine()));
+ addPass(createAtomicExpandPass());
TargetPassConfig::addIRPasses();
}