Add Octeon specific sync opcodes.

This is needed for proper sili(4) functionality on Octeon II machines.

OK jasper@, visa@

9 files changed, 37 insertions, 1 deletions

diff --git a/gnu/usr.bin/binutils-2.17/bfd/archures.c b/gnu/usr.bin/binutils-2.17/bfd/archures.c
index f4080a63a46..140eacc15d6 100644
--- a/gnu/usr.bin/binutils-2.17/bfd/archures.c
+++ b/gnu/usr.bin/binutils-2.17/bfd/archures.c
@@ -160,6 +160,7 @@ DESCRIPTION
 .#define bfd_mach_mips16		16
 .#define bfd_mach_mips5                 5
 .#define bfd_mach_mips_sb1              12310201 {* octal 'SB', 01 *}
+.#define bfd_mach_mips_octeon           6501
 .#define bfd_mach_mipsisa32             32
 .#define bfd_mach_mipsisa32r2           33
 .#define bfd_mach_mipsisa64             64
diff --git a/gnu/usr.bin/binutils-2.17/bfd/bfd-in2.h b/gnu/usr.bin/binutils-2.17/bfd/bfd-in2.h
index eafad3dd507..996449e12a5 100644
--- a/gnu/usr.bin/binutils-2.17/bfd/bfd-in2.h
+++ b/gnu/usr.bin/binutils-2.17/bfd/bfd-in2.h
@@ -1758,6 +1758,7 @@ enum bfd_architecture
 #define bfd_mach_mips16                16
 #define bfd_mach_mips5                 5
 #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01 */
+#define bfd_mach_mips_octeon           6501
 #define bfd_mach_mipsisa32             32
 #define bfd_mach_mipsisa32r2           33
 #define bfd_mach_mipsisa64             64
diff --git a/gnu/usr.bin/binutils-2.17/bfd/cpu-mips.c b/gnu/usr.bin/binutils-2.17/bfd/cpu-mips.c
index 5f4dccafbb7..524cd2097a0 100644
--- a/gnu/usr.bin/binutils-2.17/bfd/cpu-mips.c
+++ b/gnu/usr.bin/binutils-2.17/bfd/cpu-mips.c
@@ -86,6 +86,7 @@ enum
   I_mipsisa64,
   I_mipsisa64r2,
   I_sb1,
+  I_mipsocteon,
 };
 
 #define NN(index) (&arch_info_struct[(index) + 1])
@@ -118,7 +119,8 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
   N (64, 64, bfd_mach_mipsisa64,  "mips:isa64",   FALSE, NN(I_mipsisa64)),
   N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
-  N (64, 64, bfd_mach_mips_sb1, "mips:sb1",       FALSE, 0),
+  N (64, 64, bfd_mach_mips_sb1, "mips:sb1",       FALSE, NN(I_sb1)),
+  N (64, 64, bfd_mach_mips_octeon,"mips:octeon",  FALSE, 0),
 };
 
 /* The default architecture is mips:3000, but with a machine number of
diff --git a/gnu/usr.bin/binutils-2.17/bfd/elfxx-mips.c b/gnu/usr.bin/binutils-2.17/bfd/elfxx-mips.c
index b28a010a847..2f9d4a83eee 100644
--- a/gnu/usr.bin/binutils-2.17/bfd/elfxx-mips.c
+++ b/gnu/usr.bin/binutils-2.17/bfd/elfxx-mips.c
@@ -4969,6 +4969,9 @@ _bfd_elf_mips_mach (flagword flags)
     case E_MIPS_MACH_SB1:
       return bfd_mach_mips_sb1;
 
+    case E_MIPS_MACH_OCTEON:
+      return bfd_mach_mips_octeon;
+
     default:
       switch (flags & EF_MIPS_ARCH)
 	{
@@ -9035,6 +9038,10 @@ mips_set_isa_flags (bfd *abfd)
       val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
       break;
 
+    case bfd_mach_mips_octeon:
+      val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
+      break;
+
     case bfd_mach_mipsisa32:
       val = E_MIPS_ARCH_32;
       break;
@@ -10716,6 +10723,9 @@ struct mips_mach_extension {
    are ordered topologically with MIPS I extensions listed last.  */
 
 static const struct mips_mach_extension mips_mach_extensions[] = {
+  /* MIPS64r2 extensions.  */
+  { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
+
   /* MIPS64 extensions.  */
   { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
   { bfd_mach_mips_sb1, bfd_mach_mipsisa64 },
diff --git a/gnu/usr.bin/binutils-2.17/gas/config/tc-mips.c b/gnu/usr.bin/binutils-2.17/gas/config/tc-mips.c
index f982da56b93..bf8fafeab01 100644
--- a/gnu/usr.bin/binutils-2.17/gas/config/tc-mips.c
+++ b/gnu/usr.bin/binutils-2.17/gas/config/tc-mips.c
@@ -14402,6 +14402,9 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
   { "loongson2f",     0,      ISA_L2F,        CPU_L2F },
   */
 
+  /* Cavium Networks Octeon CPU core */
+  { "octeon",         0,      ISA_MIPS64R2,   CPU_OCTEON },
+
   /* MIPS IV */
   { "r8000",          0,      ISA_MIPS4,      CPU_R8000 },
   { "r10000",         0,      ISA_MIPS4,      CPU_R10000 },
diff --git a/gnu/usr.bin/binutils-2.17/include/elf/mips.h b/gnu/usr.bin/binutils-2.17/include/elf/mips.h
index f22bd4d4213..a0b1d606338 100644
--- a/gnu/usr.bin/binutils-2.17/include/elf/mips.h
+++ b/gnu/usr.bin/binutils-2.17/include/elf/mips.h
@@ -212,6 +212,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 #define E_MIPS_MACH_4120	0x00870000
 #define E_MIPS_MACH_4111	0x00880000
 #define E_MIPS_MACH_SB1         0x008a0000
+#define E_MIPS_MACH_OCTEON      0x008b0000
 #define E_MIPS_MACH_5400	0x00910000
 #define E_MIPS_MACH_5500	0x00980000
 #define E_MIPS_MACH_9000	0x00990000
diff --git a/gnu/usr.bin/binutils-2.17/include/opcode/mips.h b/gnu/usr.bin/binutils-2.17/include/opcode/mips.h
index 001d55a05ce..c32fb3a8a69 100644
--- a/gnu/usr.bin/binutils-2.17/include/opcode/mips.h
+++ b/gnu/usr.bin/binutils-2.17/include/opcode/mips.h
@@ -480,6 +480,8 @@ struct mips_opcode
 
 /* Chip specific instructions.  These are bitmasks.  */
 
+#define INSN_CHIP_MASK            0x0bff0000
+
 /* MIPS R4650 instruction.  */
 #define INSN_4650                 0x00010000
 /* LSI R4010 instruction.  */
@@ -502,6 +504,9 @@ struct mips_opcode
 #define INSN_5500		  0x02000000
 /* MT ASE */
 #define INSN_MT                   0x04000000
+/* Cavium Networks Octeon instruction.  */
+#define INSN_OCTEON               0x08000000
+
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
@@ -549,6 +554,7 @@ struct mips_opcode
 #define CPU_MIPS64      64
 #define CPU_MIPS64R2	65
 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
+#define CPU_OCTEON	6501
 
 /* Test for membership in an ISA including chip specific ISAs.  INSN
    is pointer to an element of the opcode table; ISA is the specified
@@ -570,6 +576,7 @@ struct mips_opcode
      || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)	\
      || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)	\
      || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)	\
+     || (cpu == CPU_OCTEON && ((insn)->membership & INSN_OCTEON) != 0)	\
      || 0)	/* Please keep this term for easier source merging.  */
 
 /* This is a list of macro expanded instructions.
diff --git a/gnu/usr.bin/binutils-2.17/opcodes/mips-dis.c b/gnu/usr.bin/binutils-2.17/opcodes/mips-dis.c
index 9a48d86d2d1..c0b0fbc18e0 100644
--- a/gnu/usr.bin/binutils-2.17/opcodes/mips-dis.c
+++ b/gnu/usr.bin/binutils-2.17/opcodes/mips-dis.c
@@ -394,6 +394,12 @@ const struct mips_arch_choice mips_arch_choices[] =
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_hwr_names_mips3264r2 },
 
+  { "octeon",   1, bfd_mach_mips_octeon, CPU_OCTEON,
+    ISA_MIPS64R2 | INSN_OCTEON,
+    mips_cp0_names_mips3264r2,
+    mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
+    mips_hwr_names_mips3264r2 },
+
   { "sb1",	1, bfd_mach_mips_sb1, CPU_SB1,
     ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
     mips_cp0_names_sb1,
diff --git a/gnu/usr.bin/binutils-2.17/opcodes/mips-opc.c b/gnu/usr.bin/binutils-2.17/opcodes/mips-opc.c
index f2980429351..c56d387f666 100644
--- a/gnu/usr.bin/binutils-2.17/opcodes/mips-opc.c
+++ b/gnu/usr.bin/binutils-2.17/opcodes/mips-opc.c
@@ -109,6 +109,7 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
 #define N5	(INSN_5400 | INSN_5500)
 #define N54	INSN_5400
 #define N55	INSN_5500
+#define IOCT	INSN_OCTEON
 
 #define G1      (T3             \
                  )
@@ -1182,6 +1183,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000,	RD_t|RD_b,		0,		I2	}, /* same */
 {"invalidate", "t,A(b)",0,    (int) M_SWR_AB,	INSN_MACRO,		0,		I2	}, /* as swr */
 {"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S,	0,		I4|I33	},
+{"synciobdma",	"",	0x0000008f, 0xffffffff,	INSN_SYNC,		0,		IOCT	},
+{"syncs",	"",	0x0000018f, 0xffffffff,	INSN_SYNC,		0,		IOCT	},
+{"syncw",	"",	0x0000010f, 0xffffffff,	INSN_SYNC,		0,		IOCT	},
+{"syncws",	"",	0x0000014f, 0xffffffff,	INSN_SYNC,		0,		IOCT	},
 {"sync",    "",		0x0000000f, 0xffffffff,	INSN_SYNC,		0,		I2|G1	},
 {"sync.p",  "",		0x0000040f, 0xffffffff,	INSN_SYNC,		0,		I2	},
 {"sync.l",  "",		0x0000000f, 0xffffffff,	INSN_SYNC,		0,		I2	},