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| author |   martynas <martynas@openbsd.org> | 2011-05-25 21:26:55 +0000 |
|---|---|---|
| committer | martynas <martynas@openbsd.org> | 2011-05-25 21:26:55 +0000 |
| commit | 66e02d3fb8d64208b7e23ff761389558425df954 (patch) | |
| tree | 6a543e4b8b66a4eece11117a2ee1720e73168c80 /lib/libm/man/feenableexcept.3 | |
| parent | Set UX and SX in the system register early in boot. While not necessary on (diff) | |
| download | wireguard-openbsd-66e02d3fb8d64208b7e23ff761389558425df954.tar.xz wireguard-openbsd-66e02d3fb8d64208b7e23ff761389558425df954.zip | |
On PowerPC we cannot manipulate FPSCR[VX]--it's a summary of all
the invalid exception bits, as described in Section 3.3.6.1.1 of
PowerPC Architecture Programming Environments Manual.
A proper way to cause an invalid operation exception is to set
FPSCR[VXSOFT]. Similarly, we clear all the FPSCR[VX*] bits otherwise.
Diffstat (limited to 'lib/libm/man/feenableexcept.3')
0 files changed, 0 insertions, 0 deletions