In 2013, when OpenBSD/armv7 was still rather early, improvements for

that platform have been trickling in bit by bit.  One of those
changes unfortunately introduced a regression in cache flushes.  The
check for the length in the cache-flush-loop was changed from the
instruction bpl to bhi.  This has the effect that it does not branch
on zero anymore.  Due to the length decrement at the beginning of
the function, which was not removed, a length of (n * cacheline) + 1
means that the loop misses one run!  This means it is possible that
the last byte of a DMA transfer was incorrect, as one could see on
network packets often enough.  Remove that instruction, which makes
it even more similar to the OpenBSD/arm64 code.

ok deraadt@

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