Implement ampintcmsi(4) in ampintc(4) to support MSI. The GICv2M is an

extension to the GIC controller, which is represented as subnode in the
device tree.  There can be multiple GICv2Ms, so it makes sense to attach
those to ampintc(4) as some kind of simplebus.  The GICv2M is simply an
interrupt generator that can be used by PCIe devices to ring the door
bell.  There is no need for further configuration, we only need to find
out which SPIs we are allowed to use for MSI and to register an edge
triggered interrupt on a (randomly) allocated SPI.

Implement support for interrupt types.  The GIC only seems to support
level triggered active-high or egdge triggered low-to-high interrupts.
We currently always configure them to be level triggered, which is a
sane default for most controllers.  Since MSI interupts on the GIC are
edge triggered, we need to be able to parse the type information and to
configure the interrupt correspondingly.

ok kettenis@

1 files changed, 5 insertions, 3 deletions

diff --git a/sys/arch/arm/cortex/files.cortex b/sys/arch/arm/cortex/files.cortex
index 72b0256cc35..cd5661615be 100644
--- a/sys/arch/arm/cortex/files.cortex
+++ b/sys/arch/arm/cortex/files.cortex
@@ -1,13 +1,15 @@
-#	$OpenBSD: files.cortex,v 1.6 2016/08/10 06:51:57 kettenis Exp $
+#	$OpenBSD: files.cortex,v 1.7 2018/07/09 09:51:43 patrick Exp $
 
 # ARM core
 device	cortex {}
 attach	cortex at fdt
 file	arch/arm/cortex/cortex.c		cortex
 
-device	ampintc
+device	ampintc: fdt
 attach	ampintc at fdt
-file	arch/arm/cortex/ampintc.c		ampintc
+device	ampintcmsi
+attach	ampintcmsi at fdt
+file	arch/arm/cortex/ampintc.c		ampintc | ampintcmsi
 
 device	amptimer
 attach	amptimer at cortex