Declare ci_ipl volatile to prevent the compiler from optimizing

or reordering accesses to the variable. Assume that the assembler
preserves the correct sequence of instructions, which allows the
removal of the explicit noreorder/reorder toggles from the C code.

With ci_ipl being volatile, drop mips_sync() calls that follow
the accesses of the variable. The sync is redundant as a compiler
barrier. In addition, the MIPS64 CPU designs should not need the
sync for pipeline or write buffer control. According to miod@,
the use of the instruction is a carryover from code targeting
early MIPS designs that lack tight integration with the cache
and write buffer.

Discussed with and testing help from miod@.
Tested on CN5020, CN6120, CN7130, CN7360, Loongson 2F and 3A1000,
R4400, R8000, R10000 and R16000.

1 files changed, 1 insertions, 11 deletions

diff --git a/sys/arch/octeon/dev/octcit.c b/sys/arch/octeon/dev/octcit.c
index 785cafa4019..06b79b1b2b4 100644
--- a/sys/arch/octeon/dev/octcit.c
+++ b/sys/arch/octeon/dev/octcit.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: octcit.c,v 1.5 2018/01/23 14:47:21 visa Exp $	*/
+/*	$OpenBSD: octcit.c,v 1.6 2018/02/24 11:42:31 visa Exp $	*/
 
 /*
  * Copyright (c) 2017 Visa Hankala
@@ -404,10 +404,7 @@ octcit_intr(uint32_t hwpend, struct trapframe *frame)
 	if (!ISSET(destpp, CIU3_DEST_PP_INT_INTR))
 		goto spurious;
 
-	__asm__ (".set noreorder\n");
 	ipl = ci->ci_ipl;
-	mips_sync();
-	__asm__ (".set reorder\n");
 
 	intsn = (destpp & CIU3_DEST_PP_INT_INTSN) >>
 	    CIU3_DEST_PP_INT_INTSN_SHIFT;
@@ -458,10 +455,7 @@ octcit_intr(uint32_t hwpend, struct trapframe *frame)
 			break;
 	}
 
-	__asm__ (".set noreorder\n");
 	ci->ci_ipl = ipl;
-	mips_sync();
-	__asm__ (".set reorder\n");
 
 spurious:
 	if (handled == 0)
@@ -478,11 +472,7 @@ octcit_splx(int newipl)
 	struct cpu_info *ci = curcpu();
 	unsigned int core = ci->ci_cpuid;
 
-	/* Update IPL. Order highly important! */
-	__asm__ (".set noreorder\n");
 	ci->ci_ipl = newipl;
-	mips_sync();
-	__asm__ (".set reorder\n");
 
 	if (newipl < sc->sc_minipl[ci->ci_cpuid])
 		CIU3_WR_8(sc, CIU3_IDT_PP(CIU3_IDT(core, 0)), 1ul << core);