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author | 2020-12-19 01:18:11 +0000 | |
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committer | 2020-12-19 01:18:11 +0000 | |
commit | 67129edc13c3a6e6041a2121aa8470131ca6f14d (patch) | |
tree | b7c7b3d617fbd5a822c0c78f984fb63d580293e7 /sys/dev/fdt/imxccm.c | |
parent | Add support for the i.MX8MP second ethernet. The Plus SoC not only has the (diff) | |
download | wireguard-openbsd-67129edc13c3a6e6041a2121aa8470131ca6f14d.tar.xz wireguard-openbsd-67129edc13c3a6e6041a2121aa8470131ca6f14d.zip |
Add support for the i.MX8MP PCIe clocks.
Diffstat (limited to 'sys/dev/fdt/imxccm.c')
-rw-r--r-- | sys/dev/fdt/imxccm.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/sys/dev/fdt/imxccm.c b/sys/dev/fdt/imxccm.c index 9736527fef3..c57ce40bdb8 100644 --- a/sys/dev/fdt/imxccm.c +++ b/sys/dev/fdt/imxccm.c @@ -1,4 +1,4 @@ -/* $OpenBSD: imxccm.c,v 1.25 2020/12/18 22:18:56 patrick Exp $ */ +/* $OpenBSD: imxccm.c,v 1.26 2020/12/19 01:18:11 patrick Exp $ */ /* * Copyright (c) 2012-2013 Patrick Wildt <patrick@blueri.se> * @@ -1919,6 +1919,22 @@ imxccm_set_parent(void *cookie, uint32_t *cells, uint32_t *pcells) mux |= (0x1 << sc->sc_muxs[idx].shift); HWRITE4(sc, sc->sc_muxs[idx].reg, mux); return 0; + case IMX8MP_CLK_PCIE_PHY: + if (pidx != IMX8MP_CLK_24M) + break; + mux = HREAD4(sc, sc->sc_muxs[idx].reg); + mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift); + mux |= (0x0 << sc->sc_muxs[idx].shift); + HWRITE4(sc, sc->sc_muxs[idx].reg, mux); + return 0; + case IMX8MP_CLK_PCIE_AUX: + if (pidx != IMX8MP_SYS_PLL2_50M) + break; + mux = HREAD4(sc, sc->sc_muxs[idx].reg); + mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift); + mux |= (0x2 << sc->sc_muxs[idx].shift); + HWRITE4(sc, sc->sc_muxs[idx].reg, mux); + return 0; case IMX8MP_CLK_ENET_QOS: if (pidx != IMX8MP_SYS_PLL2_125M) break; |