diff options
| author |   patrick <patrick@openbsd.org> | 2020-03-11 12:17:42 +0000 |
|---|---|---|
| committer | patrick <patrick@openbsd.org> | 2020-03-11 12:17:42 +0000 |
| commit | d7894d79588f9f3b7cb1e0f036dc3482a8ace8e9 (patch) | |
| tree | 80d9e3bc73266a60a480b2e611333ac5ed4267e6 /sys/dev/fdt/imxccm.c | |
| parent | Power domains on i.MX8MQ can reference other power domains, which (diff) | |
| download | wireguard-openbsd-d7894d79588f9f3b7cb1e0f036dc3482a8ace8e9.tar.xz wireguard-openbsd-d7894d79588f9f3b7cb1e0f036dc3482a8ace8e9.zip | |
The NXP-provided device trees used to make use of the assigned-clocks
properties to make sure that the PCIe clocks are configured correctly.
While upstreaming these into Linux mainline, those have been removed.
Instead the clock driver has the responsibility of setting these up on
attach. For us we'll just hardcode the parent and enable the setting
when we turn on the PCIe clocks.
ok kettenis@
Diffstat (limited to 'sys/dev/fdt/imxccm.c')
| -rw-r--r-- | sys/dev/fdt/imxccm.c | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/sys/dev/fdt/imxccm.c b/sys/dev/fdt/imxccm.c index 3a0bb2d6a0a..8a5d2cfea10 100644 --- a/sys/dev/fdt/imxccm.c +++ b/sys/dev/fdt/imxccm.c @@ -1,4 +1,4 @@ -/* $OpenBSD: imxccm.c,v 1.15 2019/04/01 08:49:35 patrick Exp $ */ +/* $OpenBSD: imxccm.c,v 1.16 2020/03/11 12:17:42 patrick Exp $ */ /* * Copyright (c) 2012-2013 Patrick Wildt <patrick@blueri.se> * @@ -927,6 +927,7 @@ imxccm_enable(void *cookie, uint32_t *cells, int on) { struct imxccm_softc *sc = cookie; uint32_t idx = cells[0], parent; + uint32_t pcells[2]; uint16_t reg; uint8_t pos; @@ -934,7 +935,22 @@ imxccm_enable(void *cookie, uint32_t *cells, int on) if (idx == 0) return; - if (sc->sc_gates == imx7d_gates) { + if (sc->sc_gates == imx8mq_gates) { + switch (idx) { + case IMX8MQ_CLK_PCIE1_CTRL: + case IMX8MQ_CLK_PCIE2_CTRL: + pcells[0] = sc->sc_phandle; + pcells[1] = IMX8MQ_SYS2_PLL_250M; + imxccm_set_parent(cookie, &idx, pcells); + break; + case IMX8MQ_CLK_PCIE1_PHY: + case IMX8MQ_CLK_PCIE2_PHY: + pcells[0] = sc->sc_phandle; + pcells[1] = IMX8MQ_SYS2_PLL_100M; + imxccm_set_parent(cookie, &idx, pcells); + break; + } + } else if (sc->sc_gates == imx7d_gates) { if (sc->sc_anatop == NULL) { sc->sc_anatop = regmap_bycompatible("fsl,imx7d-anatop"); KASSERT(sc->sc_anatop); |