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author | 2020-07-17 08:07:33 +0000 | |
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committer | 2020-07-17 08:07:33 +0000 | |
commit | 452daaedc6a44247dc76c56f4c33bc4131b7c50c (patch) | |
tree | 482245802e7d6304dfe90d749f5b8e7edac4f384 /sys/dev/fdt/imxgpc.c | |
parent | Add powerpc64 support; straight copy from octeon. (diff) | |
download | wireguard-openbsd-452daaedc6a44247dc76c56f4c33bc4131b7c50c.tar.xz wireguard-openbsd-452daaedc6a44247dc76c56f4c33bc4131b7c50c.zip |
Re-work intr_barrier(9) on arm64 to remove layer violation. So far we
have stored the struct cpu_info * in the wrapper around the interrupt
handler cookie, but since we can have a few layers inbetween, this does
not seem very nice. Instead have each and every interrupt controller
provide a barrier function. This means that intr_barrier(9) will in the
end be executed by the interrupt controller that actually wired the pin
to a core. And that's the only place where the information is stored.
ok kettenis@
Diffstat (limited to 'sys/dev/fdt/imxgpc.c')
-rw-r--r-- | sys/dev/fdt/imxgpc.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/sys/dev/fdt/imxgpc.c b/sys/dev/fdt/imxgpc.c index d2b367aabfb..87b2f6ae2f0 100644 --- a/sys/dev/fdt/imxgpc.c +++ b/sys/dev/fdt/imxgpc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: imxgpc.c,v 1.7 2020/04/26 13:20:41 patrick Exp $ */ +/* $OpenBSD: imxgpc.c,v 1.8 2020/07/17 08:07:34 patrick Exp $ */ /* * Copyright (c) 2016 Mark Kettenis * @@ -73,6 +73,7 @@ imxgpc_attach(struct device *parent, struct device *self, void *aux) sc->sc_ic.ic_cookie = &sc->sc_ic; sc->sc_ic.ic_establish = fdt_intr_parent_establish; sc->sc_ic.ic_disestablish = fdt_intr_parent_disestablish; + sc->sc_ic.ic_barrier = intr_barrier; fdt_intr_register(&sc->sc_ic); printf("\n"); |