Re-work intr_barrier(9) on arm64 to remove layer violation. So far we

have stored the struct cpu_info * in the wrapper around the interrupt
handler cookie, but since we can have a few layers inbetween, this does
not seem very nice.  Instead have each and every interrupt controller
provide a barrier function.  This means that intr_barrier(9) will in the
end be executed by the interrupt controller that actually wired the pin
to a core.  And that's the only place where the information is stored.

ok kettenis@

1 files changed, 15 insertions, 1 deletions

diff --git a/sys/dev/fdt/imxgpio.c b/sys/dev/fdt/imxgpio.c
index a1dab03217a..4da86aad524 100644
--- a/sys/dev/fdt/imxgpio.c
+++ b/sys/dev/fdt/imxgpio.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: imxgpio.c,v 1.4 2020/07/14 15:34:15 patrick Exp $ */
+/* $OpenBSD: imxgpio.c,v 1.5 2020/07/17 08:07:34 patrick Exp $ */
 /*
  * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
  * Copyright (c) 2012-2013 Patrick Wildt <patrick@blueri.se>
@@ -84,6 +84,7 @@ void imxgpio_intr_disestablish(void *);
 void imxgpio_recalc_ipl(struct imxgpio_softc *);
 void imxgpio_intr_enable(void *);
 void imxgpio_intr_disable(void *);
+void imxgpio_intr_barrier(void *);
 
 
 struct cfattach	imxgpio_ca = {
@@ -135,6 +136,7 @@ imxgpio_attach(struct device *parent, struct device *self, void *aux)
 	sc->sc_ic.ic_disestablish = imxgpio_intr_disestablish;
 	sc->sc_ic.ic_enable = imxgpio_intr_enable;
 	sc->sc_ic.ic_disable = imxgpio_intr_disable;
+	sc->sc_ic.ic_barrier = imxgpio_intr_barrier;
 	fdt_intr_register(&sc->sc_ic);
 
 	printf("\n");
@@ -409,3 +411,15 @@ imxgpio_intr_disable(void *cookie)
 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_IMR, mask);
 	splx(s);
 }
+
+void
+imxgpio_intr_barrier(void *cookie)
+{
+	struct intrhand		*ih = cookie;
+	struct imxgpio_softc	*sc = ih->ih_sc;
+
+	if (sc->sc_ih_h && ih->ih_irq >= 16)
+		intr_barrier(sc->sc_ih_h);
+	else if (sc->sc_ih_l)
+		intr_barrier(sc->sc_ih_l);
+}