replace Adaptec AIC-6915 Starfire driver with the fully bus_dma(9)-able

driver from NetBSD

ok brad@ reyk@

additional testing Nick Nauwelaerts

2 files changed, 2382 insertions, 0 deletions

diff --git a/sys/dev/ic/aic6915.c b/sys/dev/ic/aic6915.c
new file mode 100644
index 00000000000..9ed8b7a2e0a
--- /dev/null
+++ b/sys/dev/ic/aic6915.c
@@ -0,0 +1,1537 @@
+/*	$OpenBSD: aic6915.c,v 1.1 2006/12/06 20:07:52 martin Exp $	*/
+/*	$NetBSD: aic6915.c,v 1.15 2005/12/24 20:27:29 perry Exp $	*/
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Device driver for the Adaptec AIC-6915 (``Starfire'')
+ * 10/100 Ethernet controller.
+ */
+
+#include "bpfilter.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/timeout.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/ioctl.h>
+#include <sys/errno.h>
+#include <sys/device.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <net/if.h>
+#include <net/if_dl.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#include <netinet/if_ether.h>
+#endif
+
+#include <net/if_media.h>
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#endif
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <dev/mii/miivar.h>
+
+#include <dev/ic/aic6915.h>
+
+void	sf_start(struct ifnet *);
+void	sf_watchdog(struct ifnet *);
+int	sf_ioctl(struct ifnet *, u_long, caddr_t);
+int	sf_init(struct ifnet *);
+void	sf_stop(struct ifnet *, int);
+
+void	sf_shutdown(void *);
+
+void	sf_txintr(struct sf_softc *);
+void	sf_rxintr(struct sf_softc *);
+void	sf_stats_update(struct sf_softc *);
+
+void	sf_reset(struct sf_softc *);
+void	sf_macreset(struct sf_softc *);
+void	sf_rxdrain(struct sf_softc *);
+int	sf_add_rxbuf(struct sf_softc *, int);
+uint8_t	sf_read_eeprom(struct sf_softc *, int);
+void	sf_set_filter(struct sf_softc *);
+
+int	sf_mii_read(struct device *, int, int);
+void	sf_mii_write(struct device *, int, int, int);
+void	sf_mii_statchg(struct device *);
+
+void	sf_tick(void *);
+
+int	sf_mediachange(struct ifnet *);
+void	sf_mediastatus(struct ifnet *, struct ifmediareq *);
+
+uint32_t sf_reg_read(struct sf_softc *, bus_addr_t);
+void	sf_reg_write(struct sf_softc *, bus_addr_t , uint32_t);
+
+void	sf_set_filter_perfect(struct sf_softc *, int , uint8_t *);
+void	sf_set_filter_hash(struct sf_softc *, uint8_t *);
+
+struct cfdriver sf_cd = {
+	NULL, "sf", DV_IFNET
+};
+
+#define	sf_funcreg_read(sc, reg)					\
+	bus_space_read_4((sc)->sc_st, (sc)->sc_sh_func, (reg))
+#define	sf_funcreg_write(sc, reg, val)					\
+	bus_space_write_4((sc)->sc_st, (sc)->sc_sh_func, (reg), (val))
+
+uint32_t
+sf_reg_read(struct sf_softc *sc, bus_addr_t reg)
+{
+
+	if (__predict_false(sc->sc_iomapped)) {
+		bus_space_write_4(sc->sc_st, sc->sc_sh, SF_IndirectIoAccess,
+		    reg);
+		return (bus_space_read_4(sc->sc_st, sc->sc_sh,
+		    SF_IndirectIoDataPort));
+	}
+
+	return (bus_space_read_4(sc->sc_st, sc->sc_sh, reg));
+}
+
+void
+sf_reg_write(struct sf_softc *sc, bus_addr_t reg, uint32_t val)
+{
+
+	if (__predict_false(sc->sc_iomapped)) {
+		bus_space_write_4(sc->sc_st, sc->sc_sh, SF_IndirectIoAccess,
+		    reg);
+		bus_space_write_4(sc->sc_st, sc->sc_sh, SF_IndirectIoDataPort,
+		    val);
+		return;
+	}
+
+	bus_space_write_4(sc->sc_st, sc->sc_sh, reg, val);
+}
+
+#define	sf_genreg_read(sc, reg)						\
+	sf_reg_read((sc), (reg) + SF_GENREG_OFFSET)
+#define	sf_genreg_write(sc, reg, val)					\
+	sf_reg_write((sc), (reg) + SF_GENREG_OFFSET, (val))
+
+/*
+ * sf_attach:
+ *
+ *	Attach a Starfire interface to the system.
+ */
+void
+sf_attach(struct sf_softc *sc)
+{
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	int i, rseg, error;
+	bus_dma_segment_t seg;
+	u_int8_t enaddr[ETHER_ADDR_LEN];
+
+	timeout_set(&sc->sc_mii_timeout, sf_tick, sc);
+
+	/*
+	 * If we're I/O mapped, the functional register handle is
+	 * the same as the base handle.  If we're memory mapped,
+	 * carve off a chunk of the register space for the functional
+	 * registers, to save on arithmetic later.
+	 */
+	if (sc->sc_iomapped)
+		sc->sc_sh_func = sc->sc_sh;
+	else {
+		if ((error = bus_space_subregion(sc->sc_st, sc->sc_sh,
+		    SF_GENREG_OFFSET, SF_FUNCREG_SIZE, &sc->sc_sh_func)) != 0) {
+			printf("%s: unable to sub-region functional "
+			    "registers, error = %d\n", sc->sc_dev.dv_xname,
+			    error);
+			return;
+		}
+	}
+
+	/*
+	 * Initialize the transmit threshold for this interface.  The
+	 * manual describes the default as 4 * 16 bytes.  We start out
+	 * at 10 * 16 bytes, to avoid a bunch of initial underruns on
+	 * several platforms.
+	 */
+	sc->sc_txthresh = 10;
+
+	/*
+	 * Allocate the control data structures, and create and load the
+	 * DMA map for it.
+	 */
+	if ((error = bus_dmamem_alloc(sc->sc_dmat,
+	    sizeof(struct sf_control_data), PAGE_SIZE, 0, &seg, 1, &rseg,
+	    BUS_DMA_NOWAIT)) != 0) {
+		printf("%s: unable to allocate control data, error = %d\n",
+		    sc->sc_dev.dv_xname, error);
+		goto fail_0;
+	}
+
+	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
+	    sizeof(struct sf_control_data), (caddr_t *)&sc->sc_control_data,
+	    BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
+		printf("%s: unable to map control data, error = %d\n",
+		    sc->sc_dev.dv_xname, error);
+		goto fail_1;
+	}
+
+	if ((error = bus_dmamap_create(sc->sc_dmat,
+	    sizeof(struct sf_control_data), 1,
+	    sizeof(struct sf_control_data), 0, BUS_DMA_NOWAIT,
+	    &sc->sc_cddmamap)) != 0) {
+		printf("%s: unable to create control data DMA map, "
+		    "error = %d\n", sc->sc_dev.dv_xname, error);
+		goto fail_2;
+	}
+
+	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
+	    sc->sc_control_data, sizeof(struct sf_control_data), NULL,
+	    BUS_DMA_NOWAIT)) != 0) {
+		printf("%s: unable to load control data DMA map, error = %d\n",
+		    sc->sc_dev.dv_xname, error);
+		goto fail_3;
+	}
+
+	/*
+	 * Create the transmit buffer DMA maps.
+	 */
+	for (i = 0; i < SF_NTXDESC; i++) {
+		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
+		    SF_NTXFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT,
+		    &sc->sc_txsoft[i].ds_dmamap)) != 0) {
+			printf("%s: unable to create tx DMA map %d, "
+			    "error = %d\n", sc->sc_dev.dv_xname, i, error);
+			goto fail_4;
+		}
+	}
+
+	/*
+	 * Create the receive buffer DMA maps.
+	 */
+	for (i = 0; i < SF_NRXDESC; i++) {
+		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
+		    MCLBYTES, 0, BUS_DMA_NOWAIT,
+		    &sc->sc_rxsoft[i].ds_dmamap)) != 0) {
+			printf("%s: unable to create rx DMA map %d, "
+			    "error = %d\n", sc->sc_dev.dv_xname, i, error);
+			goto fail_5;
+		}
+	}
+
+	/*
+	 * Reset the chip to a known state.
+	 */
+	sf_reset(sc);
+
+	/*
+	 * Read the Ethernet address from the EEPROM.
+	 */
+	for (i = 0; i < ETHER_ADDR_LEN; i++)
+		enaddr[i] = sf_read_eeprom(sc, (15 + (ETHER_ADDR_LEN - 1)) - i);
+
+	printf(", address %s\n", ether_sprintf(enaddr));
+
+#ifdef DEBUG
+	if (sf_funcreg_read(sc, SF_PciDeviceConfig) & PDC_System64)
+		printf("%s: 64-bit PCI slot detected\n", sc->sc_dev.dv_xname);
+#endif
+
+	/*
+	 * Initialize our media structures and probe the MII.
+	 */
+	sc->sc_mii.mii_ifp = ifp;
+	sc->sc_mii.mii_readreg = sf_mii_read;
+	sc->sc_mii.mii_writereg = sf_mii_write;
+	sc->sc_mii.mii_statchg = sf_mii_statchg;
+	ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, sf_mediachange,
+	    sf_mediastatus);
+	mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
+	    MII_OFFSET_ANY, 0);
+	if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
+		ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
+		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
+	} else
+		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
+	bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
+	bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
+	ifp = &sc->sc_arpcom.ac_if;
+	ifp->if_softc = sc;
+	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+	ifp->if_ioctl = sf_ioctl;
+	ifp->if_start = sf_start;
+	ifp->if_watchdog = sf_watchdog;
+	ifp->if_init = sf_init;
+#ifdef NetBSD
+	ifp->if_stop = sf_stop;
+#endif
+	IFQ_SET_READY(&ifp->if_snd);
+
+	/*
+	 * Attach the interface.
+	 */
+	if_attach(ifp);
+	ether_ifattach(ifp);
+	/*
+	 * Make sure the interface is shutdown during reboot.
+	 */
+	sc->sc_sdhook = shutdownhook_establish(sf_shutdown, sc);
+	if (sc->sc_sdhook == NULL)
+		printf("%s: WARNING: unable to establish shutdown hook\n",
+		    sc->sc_dev.dv_xname);
+	 return;
+
+	/*
+	 * Free any resources we've allocated during the failed attach
+	 * attempt.  Do this in reverse order an fall through.
+	 */
+ fail_5:
+	for (i = 0; i < SF_NRXDESC; i++) {
+		if (sc->sc_rxsoft[i].ds_dmamap != NULL)
+			bus_dmamap_destroy(sc->sc_dmat,
+			    sc->sc_rxsoft[i].ds_dmamap);
+	}
+ fail_4:
+	for (i = 0; i < SF_NTXDESC; i++) {
+		if (sc->sc_txsoft[i].ds_dmamap != NULL)
+			bus_dmamap_destroy(sc->sc_dmat,
+			    sc->sc_txsoft[i].ds_dmamap);
+	}
+	bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
+ fail_3:
+	bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
+ fail_2:
+	bus_dmamem_unmap(sc->sc_dmat, (caddr_t) sc->sc_control_data,
+	    sizeof(struct sf_control_data));
+ fail_1:
+	bus_dmamem_free(sc->sc_dmat, &seg, rseg);
+ fail_0:
+	return;
+}
+
+/*
+ * sf_shutdown:
+ *
+ *	Shutdown hook -- make sure the interface is stopped at reboot.
+ */
+void
+sf_shutdown(void *arg)
+{
+	struct sf_softc *sc = arg;
+
+	sf_stop(&sc->sc_arpcom.ac_if, 1);
+}
+
+/*
+ * sf_start:		[ifnet interface function]
+ *
+ *	Start packet transmission on the interface.
+ */
+void
+sf_start(struct ifnet *ifp)
+{
+	struct sf_softc *sc = ifp->if_softc;
+	struct mbuf *m0, *m;
+	struct sf_txdesc0 *txd;
+	struct sf_descsoft *ds;
+	bus_dmamap_t dmamap;
+	int error, producer, last = -1, opending, seg;
+
+	/*
+	 * Remember the previous number of pending transmits.
+	 */
+	opending = sc->sc_txpending;
+
+	/*
+	 * Find out where we're sitting.
+	 */
+	producer = SF_TXDINDEX_TO_HOST(
+	    TDQPI_HiPrTxProducerIndex_get(
+	    sf_funcreg_read(sc, SF_TxDescQueueProducerIndex)));
+
+	/*
+	 * Loop through the send queue, setting up transmit descriptors
+	 * until we drain the queue, or use up all available transmit
+	 * descriptors.  Leave a blank one at the end for sanity's sake.
+	 */
+	while (sc->sc_txpending < (SF_NTXDESC - 1)) {
+		/*
+		 * Grab a packet off the queue.
+		 */
+		IFQ_POLL(&ifp->if_snd, m0);
+		if (m0 == NULL)
+			break;
+		m = NULL;
+
+		/*
+		 * Get the transmit descriptor.
+		 */
+		txd = &sc->sc_txdescs[producer];
+		ds = &sc->sc_txsoft[producer];
+		dmamap = ds->ds_dmamap;
+
+		/*
+		 * Load the DMA map.  If this fails, the packet either
+		 * didn't fit in the allotted number of frags, or we were
+		 * short on resources.  In this case, we'll copy and try
+		 * again.
+		 */
+		if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
+		    BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) {
+			MGETHDR(m, M_DONTWAIT, MT_DATA);
+			if (m == NULL) {
+				printf("%s: unable to allocate Tx mbuf\n",
+				    sc->sc_dev.dv_xname);
+				break;
+			}
+			if (m0->m_pkthdr.len > MHLEN) {
+				MCLGET(m, M_DONTWAIT);
+				if ((m->m_flags & M_EXT) == 0) {
+					printf("%s: unable to allocate Tx "
+					    "cluster\n", sc->sc_dev.dv_xname);
+					m_freem(m);
+					break;
+				}
+			}
+			m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
+			m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
+			error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap,
+			    m, BUS_DMA_WRITE|BUS_DMA_NOWAIT);
+			if (error) {
+				printf("%s: unable to load Tx buffer, "
+				    "error = %d\n", sc->sc_dev.dv_xname, error);
+				break;
+			}
+		}
+
+		/*
+		 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
+		 */
+		IFQ_DEQUEUE(&ifp->if_snd, m0);
+		if (m != NULL) {
+			m_freem(m0);
+			m0 = m;
+		}
+
+		/* Initialize the descriptor. */
+		txd->td_word0 =
+		    htole32(TD_W0_ID | TD_W0_CRCEN | m0->m_pkthdr.len);
+		if (producer == (SF_NTXDESC - 1))
+			txd->td_word0 |= TD_W0_END;
+		txd->td_word1 = htole32(dmamap->dm_nsegs);
+		for (seg = 0; seg < dmamap->dm_nsegs; seg++) {
+			txd->td_frags[seg].fr_addr =
+			    htole32(dmamap->dm_segs[seg].ds_addr);
+			txd->td_frags[seg].fr_len =
+			    htole32(dmamap->dm_segs[seg].ds_len);
+		}
+
+		/* Sync the descriptor and the DMA map. */
+		SF_CDTXDSYNC(sc, producer, BUS_DMASYNC_PREWRITE);
+		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
+		    BUS_DMASYNC_PREWRITE);
+
+		/*
+		 * Store a pointer to the packet so we can free it later.
+		 */
+		ds->ds_mbuf = m0;
+
+		/* Advance the Tx pointer. */
+		sc->sc_txpending++;
+		last = producer;
+		producer = SF_NEXTTX(producer);
+
+#if NBPFILTER > 0
+		/*
+		 * Pass the packet to any BPF listeners.
+		 */
+		if (ifp->if_bpf)
+			bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT);
+#endif
+	}
+
+	if (sc->sc_txpending == (SF_NTXDESC - 1)) {
+		/* No more slots left; notify upper layer. */
+		ifp->if_flags |= IFF_OACTIVE;
+	}
+
+	if (sc->sc_txpending != opending) {
+		KASSERT(last != -1);
+		/*
+		 * We enqueued packets.  Cause a transmit interrupt to
+		 * happen on the last packet we enqueued, and give the
+		 * new descriptors to the chip by writing the new
+		 * producer index.
+		 */
+		sc->sc_txdescs[last].td_word0 |= TD_W0_INTR;
+		SF_CDTXDSYNC(sc, last, BUS_DMASYNC_PREWRITE);
+
+		sf_funcreg_write(sc, SF_TxDescQueueProducerIndex,
+		    TDQPI_HiPrTxProducerIndex(SF_TXDINDEX_TO_CHIP(producer)));
+
+		/* Set a watchdog timer in case the chip flakes out. */
+		ifp->if_timer = 5;
+	}
+}
+
+/*
+ * sf_watchdog:		[ifnet interface function]
+ *
+ *	Watchdog timer handler.
+ */
+void
+sf_watchdog(struct ifnet *ifp)
+{
+	struct sf_softc *sc = ifp->if_softc;
+
+	printf("%s: device timeout\n", sc->sc_dev.dv_xname);
+	ifp->if_oerrors++;
+
+	(void) sf_init(ifp);
+
+	/* Try to get more packets going. */
+	sf_start(ifp);
+}
+
+/*
+ * sf_ioctl:		[ifnet interface function]
+ *
+ *	Handle control requests from the operator.
+ */
+int
+sf_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
+{
+	struct sf_softc *sc = (struct sf_softc *)ifp->if_softc;
+	struct ifaddr *ifa;
+	struct ifreq *ifr = (struct ifreq *) data;
+	int s, error = 1;
+
+	s = splnet();
+	if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) {
+		splx(s);
+		return (error);
+	}
+
+	switch (cmd) {
+	case SIOCSIFADDR:
+		ifa = (struct ifaddr *)data;
+		ifp->if_flags |= IFF_UP;
+#ifdef INET
+		if (ifa->ifa_addr->sa_family == AF_INET)
+			arp_ifinit(&sc->sc_arpcom, ifa);
+#endif
+		/* FALLTHROUGH */
+	case SIOCSIFFLAGS:
+		if (ifp->if_flags & IFF_UP) {
+			if (ifp->if_flags & IFF_RUNNING)
+				sf_set_filter(sc);
+			else
+				sf_init(ifp);
+		} else {
+			if (ifp->if_flags & IFF_RUNNING)
+				sf_stop(ifp, 1);
+		}
+		break;
+
+	case SIOCSIFMTU:
+		if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ifp->if_hardmtu)
+			error = EINVAL;
+		else if (ifp->if_mtu != ifr->ifr_mtu)
+			ifp->if_mtu = ifr->ifr_mtu;
+		break;
+
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		ifr = (struct ifreq *)data;
+		error = (cmd == SIOCADDMULTI) ?
+			ether_addmulti(ifr, &sc->sc_arpcom) :
+			ether_delmulti(ifr, &sc->sc_arpcom);
+
+		if (error == ENETRESET) {
+			if (ifp->if_flags & IFF_RUNNING)
+				sf_set_filter(sc);
+			error = 0;
+		}
+		break;
+
+	case SIOCGIFMEDIA:
+	case SIOCSIFMEDIA:
+		error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
+		break;
+
+	default:
+		error = ENOTTY;
+	}
+
+	if (error == ENETRESET) {
+		if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
+		    (IFF_UP | IFF_RUNNING))
+			/* Try to get more packets going. */
+			sf_start(ifp);
+		error = 0;
+	}
+
+	splx(s);
+	return (error);
+}
+
+/*
+ * sf_intr:
+ *
+ *	Interrupt service routine.
+ */
+int
+sf_intr(void *arg)
+{
+	struct sf_softc *sc = arg;
+	uint32_t isr;
+	int handled = 0, wantinit = 0;
+
+	for (;;) {
+		/* Reading clears all interrupts we're interested in. */
+		isr = sf_funcreg_read(sc, SF_InterruptStatus);
+		if ((isr & IS_PCIPadInt) == 0)
+			break;
+
+		handled = 1;
+
+		/* Handle receive interrupts. */
+		if (isr & IS_RxQ1DoneInt)
+			sf_rxintr(sc);
+
+		/* Handle transmit completion interrupts. */
+		if (isr & (IS_TxDmaDoneInt|IS_TxQueueDoneInt))
+			sf_txintr(sc);
+
+		/* Handle abnormal interrupts. */
+		if (isr & IS_AbnormalInterrupt) {
+			/* Statistics. */
+			if (isr & IS_StatisticWrapInt)
+				sf_stats_update(sc);
+
+			/* DMA errors. */
+			if (isr & IS_DmaErrInt) {
+				wantinit = 1;
+				printf("%s: WARNING: DMA error\n",
+				    sc->sc_dev.dv_xname);
+			}
+
+			/* Transmit FIFO underruns. */
+			if (isr & IS_TxDataLowInt) {
+				if (sc->sc_txthresh < 0xff)
+					sc->sc_txthresh++;
+#ifdef DEBUG
+				printf("%s: transmit FIFO underrun, new "
+				    "threshold: %d bytes\n",
+				    sc->sc_dev.dv_xname,
+				    sc->sc_txthresh * 16);
+#endif
+				sf_funcreg_write(sc, SF_TransmitFrameCSR,
+				    sc->sc_TransmitFrameCSR |
+				    TFCSR_TransmitThreshold(sc->sc_txthresh));
+				sf_funcreg_write(sc, SF_TxDescQueueCtrl,
+				    sc->sc_TxDescQueueCtrl |
+				    TDQC_TxHighPriorityFifoThreshold(
+							sc->sc_txthresh));
+			}
+		}
+	}
+
+	if (handled) {
+		/* Reset the interface, if necessary. */
+		if (wantinit)
+			sf_init(&sc->sc_arpcom.ac_if);
+
+		/* Try and get more packets going. */
+		sf_start(&sc->sc_arpcom.ac_if);
+	}
+
+	return (handled);
+}
+
+/*
+ * sf_txintr:
+ *
+ *	Helper -- handle transmit completion interrupts.
+ */
+void
+sf_txintr(struct sf_softc *sc)
+{
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	struct sf_descsoft *ds;
+	uint32_t cqci, tcd;
+	int consumer, producer, txidx;
+
+ try_again:
+	cqci = sf_funcreg_read(sc, SF_CompletionQueueConsumerIndex);
+
+	consumer = CQCI_TxCompletionConsumerIndex_get(cqci);
+	producer = CQPI_TxCompletionProducerIndex_get(
+	    sf_funcreg_read(sc, SF_CompletionQueueProducerIndex));
+
+	if (consumer == producer)
+		return;
+
+	ifp->if_flags &= ~IFF_OACTIVE;
+
+	while (consumer != producer) {
+		SF_CDTXCSYNC(sc, consumer, BUS_DMASYNC_POSTREAD);
+		tcd = letoh32(sc->sc_txcomp[consumer].tcd_word0);
+
+		txidx = SF_TCD_INDEX_TO_HOST(TCD_INDEX(tcd));
+#ifdef DIAGNOSTIC
+		if ((tcd & TCD_PR) == 0)
+			printf("%s: Tx queue mismatch, index %d\n",
+			    sc->sc_dev.dv_xname, txidx);
+#endif
+		/*
+		 * NOTE: stats are updated later.  We're just
+		 * releasing packets that have been DMA'd to
+		 * the chip.
+		 */
+		ds = &sc->sc_txsoft[txidx];
+		SF_CDTXDSYNC(sc, txidx, BUS_DMASYNC_POSTWRITE);
+		bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap,
+		    0, ds->ds_dmamap->dm_mapsize,
+		    BUS_DMASYNC_POSTWRITE);
+		m_freem(ds->ds_mbuf);
+		ds->ds_mbuf = NULL;
+
+		consumer = SF_NEXTTCD(consumer);
+		sc->sc_txpending--;
+	}
+
+	/* XXXJRT -- should be KDASSERT() */
+	KASSERT(sc->sc_txpending >= 0);
+
+	/* If all packets are done, cancel the watchdog timer. */
+	if (sc->sc_txpending == 0)
+		ifp->if_timer = 0;
+
+	/* Update the consumer index. */
+	sf_funcreg_write(sc, SF_CompletionQueueConsumerIndex,
+	    (cqci & ~CQCI_TxCompletionConsumerIndex(0x7ff)) |
+	     CQCI_TxCompletionConsumerIndex(consumer));
+
+	/* Double check for new completions. */
+	goto try_again;
+}
+
+/*
+ * sf_rxintr:
+ *
+ *	Helper -- handle receive interrupts.
+ */
+void
+sf_rxintr(struct sf_softc *sc)
+{
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	struct sf_descsoft *ds;
+	struct sf_rcd_full *rcd;
+	struct mbuf *m;
+	uint32_t cqci, word0;
+	int consumer, producer, bufproducer, rxidx, len;
+
+ try_again:
+	cqci = sf_funcreg_read(sc, SF_CompletionQueueConsumerIndex);
+
+	consumer = CQCI_RxCompletionQ1ConsumerIndex_get(cqci);
+	producer = CQPI_RxCompletionQ1ProducerIndex_get(
+	    sf_funcreg_read(sc, SF_CompletionQueueProducerIndex));
+	bufproducer = RXQ1P_RxDescQ1Producer_get(
+	    sf_funcreg_read(sc, SF_RxDescQueue1Ptrs));
+
+	if (consumer == producer)
+		return;
+
+	while (consumer != producer) {
+		rcd = &sc->sc_rxcomp[consumer];
+		SF_CDRXCSYNC(sc, consumer,
+		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
+		SF_CDRXCSYNC(sc, consumer,
+		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+
+		word0 = letoh32(rcd->rcd_word0);
+		rxidx = RCD_W0_EndIndex(word0);
+
+		ds = &sc->sc_rxsoft[rxidx];
+
+		consumer = SF_NEXTRCD(consumer);
+		bufproducer = SF_NEXTRX(bufproducer);
+
+		if ((word0 & RCD_W0_OK) == 0) {
+			SF_INIT_RXDESC(sc, rxidx);
+			continue;
+		}
+
+		bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
+		    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
+
+		/*
+		 * No errors; receive the packet.  Note that we have
+		 * configured the Starfire to NOT transfer the CRC
+		 * with the packet.
+		 */
+		len = RCD_W0_Length(word0);
+
+#ifdef __NO_STRICT_ALIGNMENT
+		/*
+		 * Allocate a new mbuf cluster.  If that fails, we are
+		 * out of memory, and must drop the packet and recycle
+		 * the buffer that's already attached to this descriptor.
+		 */
+		m = ds->ds_mbuf;
+		if (sf_add_rxbuf(sc, rxidx) != 0) {
+			ifp->if_ierrors++;
+			SF_INIT_RXDESC(sc, rxidx);
+			bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
+			    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
+			continue;
+		}
+#else
+		/*
+		 * The Starfire's receive buffer must be 4-byte aligned.
+		 * But this means that the data after the Ethernet header
+		 * is misaligned.  We must allocate a new buffer and
+		 * copy the data, shifted forward 2 bytes.
+		 */
+		MGETHDR(m, M_DONTWAIT, MT_DATA);
+		if (m == NULL) {
+ dropit:
+			ifp->if_ierrors++;
+			SF_INIT_RXDESC(sc, rxidx);
+			bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
+			    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
+			continue;
+		}
+		if (len > (MHLEN - 2)) {
+			MCLGET(m, M_DONTWAIT);
+			if ((m->m_flags & M_EXT) == 0) {
+				m_freem(m);
+				goto dropit;
+			}
+		}
+		m->m_data += 2;
+
+		/*
+		 * Note that we use cluster for incoming frames, so the
+		 * buffer is virtually contiguous.
+		 */
+		memcpy(mtod(m, caddr_t), mtod(ds->ds_mbuf, caddr_t), len);
+
+		/* Allow the receive descriptor to continue using its mbuf. */
+		SF_INIT_RXDESC(sc, rxidx);
+		bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
+		    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
+#endif /* __NO_STRICT_ALIGNMENT */
+
+		m->m_pkthdr.rcvif = ifp;
+		m->m_pkthdr.len = m->m_len = len;
+
+#if NBPFILTER > 0
+		/*
+		 * Pass this up to any BPF listeners.
+		 */
+		if (ifp->if_bpf)
+			bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
+#endif /* NBPFILTER > 0 */
+
+		/* Pass it on. */
+		ether_input_mbuf(ifp, m);
+		ifp->if_ipackets++;
+	}
+
+	/* Update the chip's pointers. */
+	sf_funcreg_write(sc, SF_CompletionQueueConsumerIndex,
+	    (cqci & ~CQCI_RxCompletionQ1ConsumerIndex(0x7ff)) |
+	     CQCI_RxCompletionQ1ConsumerIndex(consumer));
+	sf_funcreg_write(sc, SF_RxDescQueue1Ptrs,
+	    RXQ1P_RxDescQ1Producer(bufproducer));
+
+	/* Double-check for any new completions. */
+	goto try_again;
+}
+
+/*
+ * sf_tick:
+ *
+ *	One second timer, used to tick the MII and update stats.
+ */
+void
+sf_tick(void *arg)
+{
+	struct sf_softc *sc = arg;
+	int s;
+
+	s = splnet();
+	mii_tick(&sc->sc_mii);
+	sf_stats_update(sc);
+	splx(s);
+
+	timeout_add(&sc->sc_mii_timeout, hz);
+}
+
+/*
+ * sf_stats_update:
+ *
+ *	Read the statitistics counters.
+ */
+void
+sf_stats_update(struct sf_softc *sc)
+{
+	struct sf_stats stats;
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	uint32_t *p;
+	u_int i;
+
+	p = &stats.TransmitOKFrames;
+	for (i = 0; i < (sizeof(stats) / sizeof(uint32_t)); i++) {
+		*p++ = sf_genreg_read(sc,
+		    SF_STATS_BASE + (i * sizeof(uint32_t)));
+		sf_genreg_write(sc, SF_STATS_BASE + (i * sizeof(uint32_t)), 0);
+	}
+
+	ifp->if_opackets += stats.TransmitOKFrames;
+
+	ifp->if_collisions += stats.SingleCollisionFrames +
+	    stats.MultipleCollisionFrames;
+
+	ifp->if_oerrors += stats.TransmitAbortDueToExcessiveCollisions +
+	    stats.TransmitAbortDueToExcessingDeferral +
+	    stats.FramesLostDueToInternalTransmitErrors;
+
+	ifp->if_ipackets += stats.ReceiveOKFrames;
+
+	ifp->if_ierrors += stats.ReceiveCRCErrors + stats.AlignmentErrors +
+	    stats.ReceiveFramesTooLong + stats.ReceiveFramesTooShort +
+	    stats.ReceiveFramesJabbersError +
+	    stats.FramesLostDueToInternalReceiveErrors;
+}
+
+/*
+ * sf_reset:
+ *
+ *	Perform a soft reset on the Starfire.
+ */
+void
+sf_reset(struct sf_softc *sc)
+{
+	int i;
+
+	sf_funcreg_write(sc, SF_GeneralEthernetCtrl, 0);
+
+	sf_macreset(sc);
+
+	sf_funcreg_write(sc, SF_PciDeviceConfig, PDC_SoftReset);
+	for (i = 0; i < 1000; i++) {
+		delay(10);
+		if ((sf_funcreg_read(sc, SF_PciDeviceConfig) &
+		     PDC_SoftReset) == 0)
+			break;
+	}
+
+	if (i == 1000) {
+		printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname);
+		sf_funcreg_write(sc, SF_PciDeviceConfig, 0);
+	}
+
+	delay(1000);
+}
+
+/*
+ * sf_macreset:
+ *
+ *	Reset the MAC portion of the Starfire.
+ */
+void
+sf_macreset(struct sf_softc *sc)
+{
+
+	sf_genreg_write(sc, SF_MacConfig1, sc->sc_MacConfig1 | MC1_SoftRst);
+	delay(1000);
+	sf_genreg_write(sc, SF_MacConfig1, sc->sc_MacConfig1);
+}
+
+/*
+ * sf_init:		[ifnet interface function]
+ *
+ *	Initialize the interface.  Must be called at splnet().
+ */
+int
+sf_init(struct ifnet *ifp)
+{
+	struct sf_softc *sc = ifp->if_softc;
+	struct sf_descsoft *ds;
+	int error = 0;
+	u_int i;
+
+	/*
+	 * Cancel any pending I/O.
+	 */
+	sf_stop(ifp, 0);
+
+	/*
+	 * Reset the Starfire to a known state.
+	 */
+	sf_reset(sc);
+
+	/* Clear the stat counters. */
+	for (i = 0; i < sizeof(struct sf_stats); i += sizeof(uint32_t))
+		sf_genreg_write(sc, SF_STATS_BASE + i, 0);
+
+	/*
+	 * Initialize the transmit descriptor ring.
+	 */
+	memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
+	sf_funcreg_write(sc, SF_TxDescQueueHighAddr, 0);
+	sf_funcreg_write(sc, SF_HiPrTxDescQueueBaseAddr, SF_CDTXDADDR(sc, 0));
+	sf_funcreg_write(sc, SF_LoPrTxDescQueueBaseAddr, 0);
+
+	/*
+	 * Initialize the transmit completion ring.
+	 */
+	for (i = 0; i < SF_NTCD; i++) {
+		sc->sc_txcomp[i].tcd_word0 = TCD_DMA_ID;
+		SF_CDTXCSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+	}
+	sf_funcreg_write(sc, SF_CompletionQueueHighAddr, 0);
+	sf_funcreg_write(sc, SF_TxCompletionQueueCtrl, SF_CDTXCADDR(sc, 0));
+
+	/*
+	 * Initialize the receive descriptor ring.
+	 */
+	for (i = 0; i < SF_NRXDESC; i++) {
+		ds = &sc->sc_rxsoft[i];
+		if (ds->ds_mbuf == NULL) {
+			if ((error = sf_add_rxbuf(sc, i)) != 0) {
+				printf("%s: unable to allocate or map rx "
+				    "buffer %d, error = %d\n",
+				    sc->sc_dev.dv_xname, i, error);
+				/*
+				 * XXX Should attempt to run with fewer receive
+				 * XXX buffers instead of just failing.
+				 */
+				sf_rxdrain(sc);
+				goto out;
+			}
+		} else
+			SF_INIT_RXDESC(sc, i);
+	}
+	sf_funcreg_write(sc, SF_RxDescQueueHighAddress, 0);
+	sf_funcreg_write(sc, SF_RxDescQueue1LowAddress, SF_CDRXDADDR(sc, 0));
+	sf_funcreg_write(sc, SF_RxDescQueue2LowAddress, 0);
+
+	/*
+	 * Initialize the receive completion ring.
+	 */
+	for (i = 0; i < SF_NRCD; i++) {
+		sc->sc_rxcomp[i].rcd_word0 = RCD_W0_ID;
+		sc->sc_rxcomp[i].rcd_word1 = 0;
+		sc->sc_rxcomp[i].rcd_word2 = 0;
+		sc->sc_rxcomp[i].rcd_timestamp = 0;
+		SF_CDRXCSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+	}
+	sf_funcreg_write(sc, SF_RxCompletionQueue1Ctrl, SF_CDRXCADDR(sc, 0) |
+	    RCQ1C_RxCompletionQ1Type(3));
+	sf_funcreg_write(sc, SF_RxCompletionQueue2Ctrl, 0);
+
+	/*
+	 * Initialize the Tx CSR.
+	 */
+	sc->sc_TransmitFrameCSR = 0;
+	sf_funcreg_write(sc, SF_TransmitFrameCSR,
+	    sc->sc_TransmitFrameCSR |
+	    TFCSR_TransmitThreshold(sc->sc_txthresh));
+
+	/*
+	 * Initialize the Tx descriptor control register.
+	 */
+	sc->sc_TxDescQueueCtrl = TDQC_SkipLength(0) |
+	    TDQC_TxDmaBurstSize(4) |	/* default */
+	    TDQC_MinFrameSpacing(3) |	/* 128 bytes */
+	    TDQC_TxDescType(0);
+	sf_funcreg_write(sc, SF_TxDescQueueCtrl,
+	    sc->sc_TxDescQueueCtrl |
+	    TDQC_TxHighPriorityFifoThreshold(sc->sc_txthresh));
+
+	/*
+	 * Initialize the Rx descriptor control registers.
+	 */
+	sf_funcreg_write(sc, SF_RxDescQueue1Ctrl,
+	    RDQ1C_RxQ1BufferLength(MCLBYTES) |
+	    RDQ1C_RxDescSpacing(0));
+	sf_funcreg_write(sc, SF_RxDescQueue2Ctrl, 0);
+
+	/*
+	 * Initialize the Tx descriptor producer indices.
+	 */
+	sf_funcreg_write(sc, SF_TxDescQueueProducerIndex,
+	    TDQPI_HiPrTxProducerIndex(0) |
+	    TDQPI_LoPrTxProducerIndex(0));
+
+	/*
+	 * Initialize the Rx descriptor producer indices.
+	 */
+	sf_funcreg_write(sc, SF_RxDescQueue1Ptrs,
+	    RXQ1P_RxDescQ1Producer(SF_NRXDESC - 1));
+	sf_funcreg_write(sc, SF_RxDescQueue2Ptrs,
+	    RXQ2P_RxDescQ2Producer(0));
+
+	/*
+	 * Initialize the Tx and Rx completion queue consumer indices.
+	 */
+	sf_funcreg_write(sc, SF_CompletionQueueConsumerIndex,
+	    CQCI_TxCompletionConsumerIndex(0) |
+	    CQCI_RxCompletionQ1ConsumerIndex(0));
+	sf_funcreg_write(sc, SF_RxHiPrCompletionPtrs, 0);
+
+	/*
+	 * Initialize the Rx DMA control register.
+	 */
+	sf_funcreg_write(sc, SF_RxDmaCtrl,
+	    RDC_RxHighPriorityThreshold(6) |	/* default */
+	    RDC_RxBurstSize(4));		/* default */
+
+	/*
+	 * Set the receive filter.
+	 */
+	sc->sc_RxAddressFilteringCtl = 0;
+	sf_set_filter(sc);
+
+	/*
+	 * Set MacConfig1.  When we set the media, MacConfig1 will
+	 * actually be written and the MAC part reset.
+	 */
+	sc->sc_MacConfig1 = MC1_PadEn;
+
+	/*
+	 * Set the media.
+	 */
+	mii_mediachg(&sc->sc_mii);
+
+	/*
+	 * Initialize the interrupt register.
+	 */
+	sc->sc_InterruptEn = IS_PCIPadInt | IS_RxQ1DoneInt |
+	    IS_TxQueueDoneInt | IS_TxDmaDoneInt | IS_DmaErrInt |
+	    IS_StatisticWrapInt;
+	sf_funcreg_write(sc, SF_InterruptEn, sc->sc_InterruptEn);
+
+	sf_funcreg_write(sc, SF_PciDeviceConfig, PDC_IntEnable |
+	    PDC_PCIMstDmaEn | (1 << PDC_FifoThreshold_SHIFT));
+
+	/*
+	 * Start the transmit and receive processes.
+	 */
+	sf_funcreg_write(sc, SF_GeneralEthernetCtrl,
+	    GEC_TxDmaEn|GEC_RxDmaEn|GEC_TransmitEn|GEC_ReceiveEn);
+
+	/* Start the on second clock. */
+	timeout_add(&sc->sc_mii_timeout, hz);
+
+	/*
+	 * Note that the interface is now running.
+	 */
+	ifp->if_flags |= IFF_RUNNING;
+	ifp->if_flags &= ~IFF_OACTIVE;
+
+ out:
+	if (error) {
+		ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+		ifp->if_timer = 0;
+		printf("%s: interface not running\n", sc->sc_dev.dv_xname);
+	}
+	return (error);
+}
+
+/*
+ * sf_rxdrain:
+ *
+ *	Drain the receive queue.
+ */
+void
+sf_rxdrain(struct sf_softc *sc)
+{
+	struct sf_descsoft *ds;
+	int i;
+
+	for (i = 0; i < SF_NRXDESC; i++) {
+		ds = &sc->sc_rxsoft[i];
+		if (ds->ds_mbuf != NULL) {
+			bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
+			m_freem(ds->ds_mbuf);
+			ds->ds_mbuf = NULL;
+		}
+	}
+}
+
+/*
+ * sf_stop:		[ifnet interface function]
+ *
+ *	Stop transmission on the interface.
+ */
+void
+sf_stop(struct ifnet *ifp, int disable)
+{
+	struct sf_softc *sc = ifp->if_softc;
+	struct sf_descsoft *ds;
+	int i;
+
+	/* Stop the one second clock. */
+	timeout_del(&sc->sc_mii_timeout);
+
+	/* Down the MII. */
+	mii_down(&sc->sc_mii);
+
+	/* Disable interrupts. */
+	sf_funcreg_write(sc, SF_InterruptEn, 0);
+
+	/* Stop the transmit and receive processes. */
+	sf_funcreg_write(sc, SF_GeneralEthernetCtrl, 0);
+
+	/*
+	 * Release any queued transmit buffers.
+	 */
+	for (i = 0; i < SF_NTXDESC; i++) {
+		ds = &sc->sc_txsoft[i];
+		if (ds->ds_mbuf != NULL) {
+			bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
+			m_freem(ds->ds_mbuf);
+			ds->ds_mbuf = NULL;
+		}
+	}
+
+	if (disable)
+		sf_rxdrain(sc);
+
+	/*
+	 * Mark the interface down and cancel the watchdog timer.
+	 */
+	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+	ifp->if_timer = 0;
+}
+
+/*
+ * sf_read_eeprom:
+ *
+ *	Read from the Starfire EEPROM.
+ */
+uint8_t
+sf_read_eeprom(struct sf_softc *sc, int offset)
+{
+	uint32_t reg;
+
+	reg = sf_genreg_read(sc, SF_EEPROM_BASE + (offset & ~3));
+
+	return ((reg >> (8 * (offset & 3))) & 0xff);
+}
+
+/*
+ * sf_add_rxbuf:
+ *
+ *	Add a receive buffer to the indicated descriptor.
+ */
+int
+sf_add_rxbuf(struct sf_softc *sc, int idx)
+{
+	struct sf_descsoft *ds = &sc->sc_rxsoft[idx];
+	struct mbuf *m;
+	int error;
+
+	MGETHDR(m, M_DONTWAIT, MT_DATA);
+	if (m == NULL)
+		return (ENOBUFS);
+
+	MCLGET(m, M_DONTWAIT);
+	if ((m->m_flags & M_EXT) == 0) {
+		m_freem(m);
+		return (ENOBUFS);
+	}
+
+	if (ds->ds_mbuf != NULL)
+		bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
+
+	ds->ds_mbuf = m;
+
+	error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap,
+	    m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
+	    BUS_DMA_READ|BUS_DMA_NOWAIT);
+	if (error) {
+		printf("%s: can't load rx DMA map %d, error = %d\n",
+		    sc->sc_dev.dv_xname, idx, error);
+		panic("sf_add_rxbuf"); /* XXX */
+	}
+
+	bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
+	    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
+
+	SF_INIT_RXDESC(sc, idx);
+
+	return (0);
+}
+
+void
+sf_set_filter_perfect(struct sf_softc *sc, int slot, uint8_t *enaddr)
+{
+	uint32_t reg0, reg1, reg2;
+
+	reg0 = enaddr[5] | (enaddr[4] << 8);
+	reg1 = enaddr[3] | (enaddr[2] << 8);
+	reg2 = enaddr[1] | (enaddr[0] << 8);
+
+	sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 0, reg0);
+	sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 4, reg1);
+	sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 8, reg2);
+}
+
+void
+sf_set_filter_hash(struct sf_softc *sc, uint8_t *enaddr)
+{
+	uint32_t hash, slot, reg;
+
+	hash = ether_crc32_be(enaddr, ETHER_ADDR_LEN) >> 23;
+	slot = hash >> 4;
+
+	reg = sf_genreg_read(sc, SF_HASH_BASE + (slot * 0x10));
+	reg |= 1 << (hash & 0xf);
+	sf_genreg_write(sc, SF_HASH_BASE + (slot * 0x10), reg);
+}
+
+/*
+ * sf_set_filter:
+ *
+ *	Set the Starfire receive filter.
+ */
+void
+sf_set_filter(struct sf_softc *sc)
+{
+	struct arpcom *ac = &sc->sc_arpcom;
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	struct ether_multi *enm;
+	struct ether_multistep step;
+	int i;
+
+	/* Start by clearing the perfect and hash tables. */
+	for (i = 0; i < SF_PERFECT_SIZE; i += sizeof(uint32_t))
+		sf_genreg_write(sc, SF_PERFECT_BASE + i, 0);
+
+	for (i = 0; i < SF_HASH_SIZE; i += sizeof(uint32_t))
+		sf_genreg_write(sc, SF_HASH_BASE + i, 0);
+
+	/*
+	 * Clear the perfect and hash mode bits.
+	 */
+	sc->sc_RxAddressFilteringCtl &=
+	    ~(RAFC_PerfectFilteringMode(3) | RAFC_HashFilteringMode(3));
+
+	if (ifp->if_flags & IFF_BROADCAST)
+		sc->sc_RxAddressFilteringCtl |= RAFC_PassBroadcast;
+	else
+		sc->sc_RxAddressFilteringCtl &= ~RAFC_PassBroadcast;
+
+	if (ifp->if_flags & IFF_PROMISC) {
+		sc->sc_RxAddressFilteringCtl |= RAFC_PromiscuousMode;
+		goto allmulti;
+	} else
+		sc->sc_RxAddressFilteringCtl &= ~RAFC_PromiscuousMode;
+
+	/*
+	 * Set normal perfect filtering mode.
+	 */
+	sc->sc_RxAddressFilteringCtl |= RAFC_PerfectFilteringMode(1);
+
+	/*
+	 * First, write the station address to the perfect filter
+	 * table.
+	 */
+	sf_set_filter_perfect(sc, 0, LLADDR(ifp->if_sadl));
+
+	/*
+	 * Now set the hash bits for each multicast address in our
+	 * list.
+	 */
+	ETHER_FIRST_MULTI(step, ac, enm);
+	if (enm == NULL)
+		goto done;
+	while (enm != NULL) {
+		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
+			/*
+			 * We must listen to a range of multicast addresses.
+			 * For now, just accept all multicasts, rather than
+			 * trying to set only those filter bits needed to match
+			 * the range.  (At this time, the only use of address
+			 * ranges is for IP multicast routing, for which the
+			 * range is big enough to require all bits set.)
+			 */
+			goto allmulti;
+		}
+		sf_set_filter_hash(sc, enm->enm_addrlo);
+		ETHER_NEXT_MULTI(step, enm);
+	}
+
+	/*
+	 * Set "hash only multicast dest, match regardless of VLAN ID".
+	 */
+	sc->sc_RxAddressFilteringCtl |= RAFC_HashFilteringMode(2);
+	goto done;
+
+ allmulti:
+	/*
+	 * XXX RAFC_PassMulticast is sub-optimal if using VLAN mode.
+	 */
+	sc->sc_RxAddressFilteringCtl |= RAFC_PassMulticast;
+	ifp->if_flags |= IFF_ALLMULTI;
+
+ done:
+	sf_funcreg_write(sc, SF_RxAddressFilteringCtl,
+	    sc->sc_RxAddressFilteringCtl);
+}
+
+/*
+ * sf_mii_read:		[mii interface function]
+ *
+ *	Read from the MII.
+ */
+int
+sf_mii_read(struct device *self, int phy, int reg)
+{
+	struct sf_softc *sc = (void *) self;
+	uint32_t v;
+	int i;
+
+	for (i = 0; i < 1000; i++) {
+		v = sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg));
+		if (v & MiiDataValid)
+			break;
+		delay(1);
+	}
+
+	if ((v & MiiDataValid) == 0)
+		return (0);
+
+	if (MiiRegDataPort(v) == 0xffff)
+		return (0);
+
+	return (MiiRegDataPort(v));
+}
+
+/*
+ * sf_mii_write:	[mii interface function]
+ *
+ *	Write to the MII.
+ */
+void
+sf_mii_write(struct device *self, int phy, int reg, int val)
+{
+	struct sf_softc *sc = (void *) self;
+	int i;
+
+	sf_genreg_write(sc, SF_MII_PHY_REG(phy, reg), val);
+
+	for (i = 0; i < 1000; i++) {
+		if ((sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg)) &
+		     MiiBusy) == 0)
+			return;
+		delay(1);
+	}
+
+	printf("%s: MII write timed out\n", sc->sc_dev.dv_xname);
+}
+
+/*
+ * sf_mii_statchg:	[mii interface function]
+ *
+ *	Callback from the PHY when the media changes.
+ */
+void
+sf_mii_statchg(struct device *self)
+{
+	struct sf_softc *sc = (void *) self;
+	uint32_t ipg;
+
+	if (sc->sc_mii.mii_media_active & IFM_FDX) {
+		sc->sc_MacConfig1 |= MC1_FullDuplex;
+		ipg = 0x15;
+	} else {
+		sc->sc_MacConfig1 &= ~MC1_FullDuplex;
+		ipg = 0x11;
+	}
+
+	sf_genreg_write(sc, SF_MacConfig1, sc->sc_MacConfig1);
+	sf_macreset(sc);
+
+	sf_genreg_write(sc, SF_BkToBkIPG, ipg);
+}
+
+/*
+ * sf_mediastatus:	[ifmedia interface function]
+ *
+ *	Callback from ifmedia to request current media status.
+ */
+void
+sf_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+	struct sf_softc *sc = ifp->if_softc;
+
+	mii_pollstat(&sc->sc_mii);
+	ifmr->ifm_status = sc->sc_mii.mii_media_status;
+	ifmr->ifm_active = sc->sc_mii.mii_media_active;
+}
+
+/*
+ * sf_mediachange:	[ifmedia interface function]
+ *
+ *	Callback from ifmedia to request new media setting.
+ */
+int
+sf_mediachange(struct ifnet *ifp)
+{
+	struct sf_softc *sc = ifp->if_softc;
+
+	if (ifp->if_flags & IFF_UP)
+		mii_mediachg(&sc->sc_mii);
+	return (0);
+}
diff --git a/sys/dev/ic/aic6915.h b/sys/dev/ic/aic6915.h
new file mode 100644
index 00000000000..fd5f07be5a8
--- /dev/null
+++ b/sys/dev/ic/aic6915.h
@@ -0,0 +1,845 @@
+/*	$OpenBSD: aic6915.h,v 1.1 2006/12/06 20:07:52 martin Exp $	*/
+/*	$NetBSD: aic6915reg.h,v 1.4 2005/12/11 12:21:25 christos Exp $	*/
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_IC_AIC6915_H_
+#define	_DEV_IC_AIC6915_H_
+
+#include <sys/timeout.h>
+
+/*
+ * Register description for the Adaptec AIC-6915 (``Starfire'')
+ * 10/100 Ethernet controller.
+ */
+
+/*
+ * Receive Buffer Descriptor (One-size, 32-bit addressing)
+ */
+struct sf_rbd32 {
+	uint32_t	rbd32_addr;		/* address, flags */
+};
+
+/*
+ * Receive Buffer Descriptor (One-size, 64-bit addressing)
+ */
+struct sf_rbd64 {
+	uint32_t	rbd64_addr_lo;		/* address (LSD), flags */
+	uint32_t	rbd64_addr_hi;		/* address (MDS) */
+};
+
+#define	RBD_V		(1U << 0)	/* valid descriptor */
+#define	RBD_E		(1U << 1)	/* end of ring */
+
+/*
+ * Short (Type 0) Completion Descriptor
+ */
+struct sf_rcd_short {
+	uint32_t	rcd_word0;	/* length, end index, status1 */
+};
+
+/*
+ * Basic (Type 1) Completion Descriptor
+ */
+struct sf_rcd_basic {
+	uint32_t	rcd_word0;	/* length, end index, status1 */
+	uint32_t	rcd_word1;	/* VLAN ID, status2 */
+};
+
+/*
+ * Checksum (Type 2) Completion Descriptor
+ */
+struct sf_rcd_checksum {
+	uint32_t	rcd_word0;	/* length, end index, status1 */
+	uint32_t	rcd_word1;	/* partial TCP/UDP checksum, status2 */
+};
+
+/*
+ * Full (Type 3) Completion Descriptor
+ */
+struct sf_rcd_full {
+	uint32_t	rcd_word0;	/* length, end index, status1 */
+	uint32_t	rcd_word1;	/* start index, status3, status2 */
+	uint32_t	rcd_word2;	/* VLAN ID + priority, TCP/UDP csum */
+	uint32_t	rcd_timestamp;	/* timestamp */
+};
+
+#define	RCD_W0_ID		(1U << 30)
+
+#define	RCD_W0_Length(x)	((x) & 0xffff)
+#define	RCD_W0_EndIndex(x)	(((x) >> 16) & 0x7ff)
+#define	RCD_W0_BufferQueue	(1U << 27)	/* 1 == Queue 2 */
+#define	RCD_W0_FifoFull		(1U << 28)	/* FIFO full */
+#define	RCD_W0_OK		(1U << 29)	/* packet is OK */
+
+/* Status2 field */
+#define	RCD_W1_FrameType	(7U << 16)
+#define	RCD_W1_FrameType_Unknown (0 << 16)
+#define	RCD_W1_FrameType_IPv4	(1U << 16)
+#define	RCD_W1_FrameType_IPv6	(2U << 16)
+#define	RCD_W1_FrameType_IPX	(3U << 16)
+#define	RCD_W1_FrameType_ICMP	(4U << 16)
+#define	RCD_W1_FrameType_Unsupported (5U << 16)
+#define	RCD_W1_UdpFrame		(1U << 19)
+#define	RCD_W1_TcpFrame		(1U << 20)
+#define	RCD_W1_Fragmented	(1U << 21)
+#define	RCD_W1_PartialChecksumValid (1U << 22)
+#define	RCD_W1_ChecksumBad	(1U << 23)
+#define	RCD_W1_ChecksumOk	(1U << 24)
+#define	RCD_W1_VlanFrame	(1U << 25)
+#define	RCD_W1_ReceiveCodeViolation (1U << 26)
+#define	RCD_W1_Dribble		(1U << 27)
+#define	RCD_W1_ISLCRCerror	(1U << 28)
+#define	RCD_W1_CRCerror		(1U << 29)
+#define	RCD_W1_Hash		(1U << 30)
+#define	RCD_W1_Perfect		(1U << 31)
+
+#define	RCD_W1_VLANID(x)	((x) & 0xffff)
+#define	RCD_W1_TCP_UDP_Checksum(x) ((x) & 0xffff)
+
+/* Status3 field */
+#define	RCD_W1_Trailer		(1U << 11)
+#define	RCD_W1_Header		(1U << 12)
+#define	RCD_W1_ControlFrame	(1U << 13)
+#define	RCD_W1_PauseFrame	(1U << 14)
+#define	RCD_W1_IslFrame		(1U << 15)
+
+#define	RCD_W1_StartIndex(x)	((x) & 0x7ff)
+
+#define	RCD_W2_TCP_UDP_Checksum(x) ((x) >> 16)
+#define	RCD_W2_VLANID(x)	((x) & 0xffff)
+
+/*
+ * Number of transmit buffer fragments we use.  This is arbitrary, but
+ * we choose it carefully; see blow.
+ */
+#define	SF_NTXFRAGS		15
+
+/*
+ * Type 0, 32-bit addressing mode (Frame Descriptor) Transmit Descriptor
+ *
+ * NOTE: The total length of this structure is: 8 + (15 * 8) == 128
+ * This means 16 Tx indices per Type 0 descriptor.  This is important later
+ * on; see below.
+ */
+struct sf_txdesc0 {
+	/* skip field */
+	uint32_t	td_word0;	/* ID, flags */
+	uint32_t	td_word1;	/* Tx buffer count */
+	struct {
+		uint32_t fr_addr;	/* address */
+		uint32_t fr_len;	/* length */
+	} td_frags[SF_NTXFRAGS];
+};
+
+#define	TD_W1_NTXBUFS		(0xff << 0)
+
+/*
+ * Type 1, 32-bit addressing mode (Buffer Descriptor) Transmit Descriptor
+ */
+struct sf_txdesc1 {
+	/* skip field */
+	uint32_t	td_word0;	/* ID, flags */
+	uint32_t	td_addr;	/* buffer address */
+};
+
+#define	TD_W0_ID		(0xb << 28)
+#define	TD_W0_INTR		(1U << 27)
+#define	TD_W0_END		(1U << 26)
+#define	TD_W0_CALTCP		(1U << 25)
+#define	TD_W0_CRCEN		(1U << 24)
+#define	TD_W0_LEN		(0xffff << 0)
+#define	TD_W0_NTXBUFS		(0xff << 16)
+#define	TD_W0_NTXBUFS_SHIFT	16
+
+/*
+ * Type 2, 64-bit addressing mode (Buffer Descriptor) Transmit Descriptor
+ */
+struct sf_txdesc2 {
+	/* skip field */
+	uint32_t	td_word0;	/* ID, flags */
+	uint32_t	td_reserved;
+	uint32_t	td_addr_lo;	/* buffer address (LSD) */
+	uint32_t	td_addr_hi;	/* buffer address (MSD) */
+};
+
+/*
+ * Transmit Completion Descriptor.
+ */
+struct sf_tcd {
+	uint32_t	tcd_word0;	/* index, priority, flags */
+};
+
+#define	TCD_DMA_ID		(0x4 << 29)
+#define	TCD_INDEX(x)		((x) & 0x7fff)
+#define	TCD_PR			(1U << 15)
+#define	TCD_TIMESTAMP(x)	(((x) >> 16) & 0x1fff)
+
+#define	TCD_TX_ID		(0x5 << 29)
+#define	TCD_CRCerror		(1U << 16)
+#define	TCD_FieldLengthCkError	(1U << 17)
+#define	TCD_FieldLengthRngError	(1U << 18)
+#define	TCD_PacketTxOk		(1U << 19)
+#define	TCD_Deferred		(1U << 20)
+#define	TCD_ExDeferral		(1U << 21)
+#define	TCD_ExCollisions	(1U << 22)
+#define	TCD_LateCollision	(1U << 23)
+#define	TCD_LongFrame		(1U << 24)
+#define	TCD_FIFOUnderrun	(1U << 25)
+#define	TCD_ControlTx		(1U << 26)
+#define	TCD_PauseTx		(1U << 27)
+#define	TCD_TxPaused		(1U << 28)
+
+/*
+ * The Tx indices are in units of 8 bytes, and since we are using
+ * Tx descriptors that are 128 bytes long, we need to divide by 16
+ * to get the actual index that we care about.
+ */
+#define	SF_TXDINDEX_TO_HOST(x)		((x) >> 4)
+#define	SF_TXDINDEX_TO_CHIP(x)		((x) << 4)
+
+/*
+ * To make matters worse, the manual lies about the indices in the
+ * completion queue entires.  It claims they are in 8-byte units,
+ * but they're actually *BYTES*, which means we need to divide by
+ * 128 to get the actual index.
+ */
+#define	SF_TCD_INDEX_TO_HOST(x)		((x) >> 7)
+
+/*
+ * PCI configuration space addresses.
+ */
+#define	SF_PCI_MEMBA		(PCI_MAPREG_START + 0x00)
+#define	SF_PCI_IOBA		(PCI_MAPREG_START + 0x08)
+
+#define	SF_GENREG_OFFSET	0x50000
+#define	SF_FUNCREG_SIZE		0x100
+
+/*
+ * PCI functional registers.
+ */
+#define	SF_PciDeviceConfig	0x40
+#define	PDC_EnDpeInt		(1U << 31)	/* enable DPE PCIint */
+#define	PDC_EnSseInt		(1U << 30)	/* enable SSE PCIint */
+#define	PDC_EnRmaInt		(1U << 29)	/* enable RMA PCIint */
+#define	PDC_EnRtaInt		(1U << 28)	/* enable RTA PCIint */
+#define	PDC_EnStaInt		(1U << 27)	/* enable STA PCIint */
+#define	PDC_EnDprInt		(1U << 24)	/* enable DPR PCIint */
+#define	PDC_IntEnable		(1U << 23)	/* enable PCI_INTA_ */
+#define	PDC_ExternalRegCsWidth	(7U << 20)	/* external chip-sel width */
+#define	PDC_StopMWrOnCacheLineDis (1U << 19)
+#define	PDC_EpromCsWidth	(7U << 16)
+#define	PDC_EnBeLogic		(1U << 15)
+#define	PDC_LatencyStopOnCacheLine (1U << 14)
+#define	PDC_PCIMstDmaEn		(1U << 13)
+#define	PDC_StopOnCachelineEn	(1U << 12)
+#define	PDC_FifoThreshold	(0xf << 8)
+#define	PDC_FifoThreshold_SHIFT	8
+#define	PDC_MemRdCmdEn		(1U << 7)
+#define	PDC_StopOnPerr		(1U << 6)
+#define	PDC_AbortOnAddrParityErr (1U << 5)
+#define	PDC_EnIncrement		(1U << 4)
+#define	PDC_System64		(1U << 2)
+#define	PDC_Force64		(1U << 1)
+#define	PDC_SoftReset		(1U << 0)
+
+#define	SF_BacControl		0x44
+#define	BC_DescSwapMode		(0x3 << 6)
+#define	BC_DataSwapMode		(0x3 << 4)
+#define	BC_SingleDmaMode	(1U << 3)
+#define	BC_PreferTxDmaReq	(1U << 2)
+#define	BC_PreferRxDmaReq	(1U << 1)
+#define	BC_BacDmaEn		(1U << 0)
+
+#define	SF_PciMonitor1		0x48
+
+#define	SF_PciMonitor2		0x4c
+
+#define	SF_PMC			0x50
+
+#define	SF_PMCSR		0x54
+
+#define	SF_PMEvent		0x58
+
+#define	SF_SerialEpromControl	0x60
+#define	SEC_InitDone		(1U << 3)
+#define	SEC_Idle		(1U << 2)
+#define	SEC_WriteEnable		(1U << 1)
+#define	SEC_WriteDisable	(1U << 0)
+
+#define	SF_PciComplianceTesting	0x64
+
+#define	SF_IndirectIoAccess	0x68
+
+#define	SF_IndirectIoDataPort	0x6c
+
+/*
+ * Ethernet functional registers.
+ */
+#define	SF_GeneralEthernetCtrl	0x70
+#define	GEC_SetSoftInt		(1U << 8)
+#define	GEC_TxGfpEn		(1U << 5)
+#define	GEC_RxGfpEn		(1U << 4)
+#define	GEC_TxDmaEn		(1U << 3)
+#define	GEC_RxDmaEn		(1U << 2)
+#define	GEC_TransmitEn		(1U << 1)
+#define	GEC_ReceiveEn		(1U << 0)
+
+#define	SF_TimersControl	0x74
+#define	TC_EarlyRxQ1IntDelayDisable	(1U << 31)
+#define	TC_RxQ1DoneIntDelayDisable	(1U << 30)
+#define	TC_EarlyRxQ2IntDelayDisable	(1U << 29)
+#define	TC_RxQ2DoneIntDelayDisable	(1U << 28)
+#define	TC_TimeStampResolution		(1U << 26)
+#define	TC_GeneralTimerResolution	(1U << 25)
+#define	TC_OneShotMode			(1U << 24)
+#define	TC_GeneralTimerInterval		(0xff << 16)
+#define	TC_GeneralTimerInterval_SHIFT	16
+#define	TC_TxFrameCompleteIntDelayDisable (1U << 15)
+#define	TC_TxQueueDoneIntDelayDisable	(1U << 14)
+#define	TC_TxDmaDoneIntDelayDisable	(1U << 13)
+#define	TC_RxHiPrBypass			(1U << 12)
+#define	TC_Timer10X			(1U << 11)
+#define	TC_SmallRxFrame			(3U << 9)
+#define	TC_SmallFrameBypass		(1U << 8)
+#define	TC_IntMaskMode			(3U << 5)
+#define	TC_IntMaskPeriod		(0x1f << 0)
+
+#define	SF_CurrentTime		0x78
+
+#define	SF_InterruptStatus	0x80
+#define	IS_GPIO3			(1U << 31)
+#define	IS_GPIO2			(1U << 30)
+#define	IS_GPIO1			(1U << 29)
+#define	IS_GPIO0			(1U << 28)
+#define	IS_StatisticWrapInt		(1U << 27)
+#define	IS_AbnormalInterrupt		(1U << 25)
+#define	IS_GeneralTimerInt		(1U << 24)
+#define	IS_SoftInt			(1U << 23)
+#define	IS_RxCompletionQueue1Int	(1U << 22)
+#define	IS_TxCompletionQueueInt		(1U << 21)
+#define	IS_PCIInt			(1U << 20)
+#define	IS_DmaErrInt			(1U << 19)
+#define	IS_TxDataLowInt			(1U << 18)
+#define	IS_RxCompletionQueue2Int	(1U << 17)
+#define	IS_RxQ1LowBuffersInt		(1U << 16)
+#define	IS_NormalInterrupt		(1U << 15)
+#define	IS_TxFrameCompleteInt		(1U << 14)
+#define	IS_TxDmaDoneInt			(1U << 13)
+#define	IS_TxQueueDoneInt		(1U << 12)
+#define	IS_EarlyRxQ2Int			(1U << 11)
+#define	IS_EarlyRxQ1Int			(1U << 10)
+#define	IS_RxQ2DoneInt			(1U << 9)
+#define	IS_RxQ1DoneInt			(1U << 8)
+#define	IS_RxGfpNoResponseInt		(1U << 7)
+#define	IS_RxQ2LowBuffersInt		(1U << 6)
+#define	IS_NoTxChecksumInt		(1U << 5)
+#define	IS_TxLowPrMismatchInt		(1U << 4)
+#define	IS_TxHiPrMismatchInt		(1U << 3)
+#define	IS_GfpRxInt			(1U << 2)
+#define	IS_GfpTxInt			(1U << 1)
+#define	IS_PCIPadInt			(1U << 0)
+
+#define	SF_ShadowInterruptStatus 0x84
+
+#define	SF_InterruptEn		0x88
+
+#define	SF_GPIO			0x8c
+#define	GPIOCtrl(x)		(1U << (24 + (x)))
+#define	GPIOOutMode(x)		(1U << (16 + (x)))
+#define	GPIOInpMode(x, y)	((y) << (8 + ((x) * 2)))
+#define	GPIOData(x)		(1U << (x))
+
+#define	SF_TxDescQueueCtrl	0x90
+#define	TDQC_TxHighPriorityFifoThreshold(x)	((x) << 24)
+#define	TDQC_SkipLength(x)			((x) << 16)
+#define	TDQC_TxDmaBurstSize(x)			((x) << 8)
+#define	TDQC_TxDescQueue64bitAddr		(1U << 7)
+#define	TDQC_MinFrameSpacing(x)			((x) << 4)
+#define	TDQC_DisableTxDmaCompletion		(1U << 3)
+#define	TDQC_TxDescType(x)			((x) << 0)
+
+#define	SF_HiPrTxDescQueueBaseAddr 0x94
+
+#define	SF_LoPrTxDescQueueBaseAddr 0x98
+
+#define	SF_TxDescQueueHighAddr	0x9c
+
+#define	SF_TxDescQueueProducerIndex 0xa0
+#define	TDQPI_HiPrTxProducerIndex(x)		((x) << 16)
+#define	TDQPI_LoPrTxProducerIndex(x)		((x) << 0)
+#define	TDQPI_HiPrTxProducerIndex_get(x)	(((x) >> 16) & 0x7ff)
+#define	TDQPI_LoPrTxProducerIndex_get(x)	(((x) >> 0) & 0x7ff)
+
+#define	SF_TxDescQueueConsumerIndex 0xa4
+#define	TDQCI_HiPrTxConsumerIndex(x)		(((x) >> 16) & 0x7ff)
+#define	TDQCI_LoPrTxConsumerIndex(s)		(((x) >> 0) & 0x7ff)
+
+#define	SF_TxDmaStatus1		0xa8
+
+#define	SF_TxDmaStatus2		0xac
+
+#define	SF_TransmitFrameCSR	0xb0
+#define	TFCSR_TxFrameStatus			(0xff << 16)
+#define	TFCSR_TxDebugConfigBits			(0x7f << 9)
+#define	TFCSR_DmaCompletionAfterTransmitComplete (1U << 8)
+#define	TFCSR_TransmitThreshold(x)		((x) << 0)
+
+#define	SF_CompletionQueueHighAddr 0xb4
+
+#define	SF_TxCompletionQueueCtrl 0xb8
+#define	TCQC_TxCompletionBaseAddress		0xffffff00
+#define	TCQC_TxCompletion64bitAddress		(1U << 7)
+#define	TCQC_TxCompletionProducerWe		(1U << 6)
+#define	TCQC_TxCompletionSize			(1U << 5)
+#define	TCQC_CommonQueueMode			(1U << 4)
+#define	TCQC_TxCompletionQueueThreshold		((x) << 0)
+
+#define	SF_RxCompletionQueue1Ctrl 0xbc
+#define	RCQ1C_RxCompletionQ1BaseAddress		0xffffff00
+#define	RCQ1C_RxCompletionQ164bitAddress	(1U << 7)
+#define	RCQ1C_RxCompletionQ1ProducerWe		(1U << 6)
+#define	RCQ1C_RxCompletionQ1Type(x)		((x) << 4)
+#define	RCQ1C_RxCompletionQ1Threshold(x)	((x) << 0)
+
+#define	SF_RxCompletionQueue2Ctrl 0xc0
+#define	RCQ1C_RxCompletionQ2BaseAddress		0xffffff00
+#define	RCQ1C_RxCompletionQ264bitAddress	(1U << 7)
+#define	RCQ1C_RxCompletionQ2ProducerWe		(1U << 6)
+#define	RCQ1C_RxCompletionQ2Type(x)		((x) << 4)
+#define	RCQ1C_RxCompletionQ2Threshold(x)	((x) << 0)
+
+#define	SF_CompletionQueueConsumerIndex 0xc4
+#define	CQCI_TxCompletionThresholdMode		(1U << 31)
+#define	CQCI_TxCompletionConsumerIndex(x)	((x) << 16)
+#define	CQCI_TxCompletionConsumerIndex_get(x)	(((x) >> 16) & 0x7ff)
+#define	CQCI_RxCompletionQ1ThresholdMode	(1U << 15)
+#define	CQCI_RxCompletionQ1ConsumerIndex(x)	((x) << 0)
+#define	CQCI_RxCompletionQ1ConsumerIndex_get(x)	((x) & 0x7ff)
+
+#define	SF_CompletionQueueProducerIndex 0xc8
+#define	CQPI_TxCompletionProducerIndex(x)	((x) << 16)
+#define	CQPI_TxCompletionProducerIndex_get(x)	(((x) >> 16) & 0x7ff)
+#define	CQPI_RxCompletionQ1ProducerIndex(x)	((x) << 0)
+#define	CQPI_RxCompletionQ1ProducerIndex_get(x)	((x) & 0x7ff)
+
+#define	SF_RxHiPrCompletionPtrs	0xcc
+#define	RHPCP_RxCompletionQ2ProducerIndex(x)	((x) << 16)
+#define	RHPCP_RxCompletionQ2ThresholdMode	(1U << 15)
+#define	RHPCP_RxCompletionQ2ConsumerIndex(x)	((x) << 0)
+
+#define	SF_RxDmaCtrl		0xd0
+#define	RDC_RxReportBadFrames			(1U << 31)
+#define	RDC_RxDmaShortFrames			(1U << 30)
+#define	RDC_RxDmaBadFrames			(1U << 29)
+#define	RDC_RxDmaCrcErrorFrames			(1U << 28)
+#define	RDC_RxDmaControlFrame			(1U << 27)
+#define	RDC_RxDmaPauseFrame			(1U << 26)
+#define	RDC_RxChecksumMode(x)			((x) << 24)
+#define	RDC_RxCompletionQ2Enable		(1U << 23)
+#define	RDC_RxDmaQueueMode(x)			((x) << 20)
+#define	RDC_RxUseBackupQueue			(1U << 19)
+#define	RDC_RxDmaCrc				(1U << 18)
+#define	RDC_RxEarlyIntThreshold(x)		((x) << 12)
+#define	RDC_RxHighPriorityThreshold(x)		((x) << 8)
+#define	RDC_RxBurstSize(x)			((x) << 0)
+
+#define	SF_RxDescQueue1Ctrl	0xd4
+#define	RDQ1C_RxQ1BufferLength(x)		((x) << 16)
+#define	RDQ1C_RxPrefetchDescriptorsMode		(1U << 15)
+#define	RDQ1C_RxDescQ1Entries			(1U << 14)
+#define	RDQ1C_RxVariableSizeQueues		(1U << 13)
+#define	RDQ1C_Rx64bitBufferAddresses		(1U << 12)
+#define	RDQ1C_Rx64bitDescQueueAddress		(1U << 11)
+#define	RDQ1C_RxDescSpacing(x)			((x) << 8)
+#define	RDQ1C_RxQ1ConsumerWe			(1U << 7)
+#define	RDQ1C_RxQ1MinDescriptorsThreshold(x)	((x) << 0)
+
+#define	SF_RxDescQueue2Ctrl	0xd8
+#define	RDQ2C_RxQ2BufferLength(x)		((x) << 16)
+#define	RDQ2C_RxDescQ2Entries			(1U << 14)
+#define	RDQ2C_RxQ2MinDescriptorsThreshold(x)	((x) << 0)
+
+#define	SF_RxDescQueueHighAddress 0xdc
+
+#define	SF_RxDescQueue1LowAddress 0xe0
+
+#define	SF_RxDescQueue2LowAddress 0xe4
+
+#define	SF_RxDescQueue1Ptrs	0xe8
+#define	RXQ1P_RxDescQ1Consumer(x)		((x) << 16)
+#define	RXQ1P_RxDescQ1Producer(x)		((x) << 0)
+#define	RXQ1P_RxDescQ1Producer_get(x)		((x) & 0x7ff)
+
+#define	SF_RxDescQueue2Ptrs	0xec
+#define	RXQ2P_RxDescQ2Consumer(x)		((x) << 16)
+#define	RXQ2P_RxDescQ2Producer(x)		((x) << 0)
+
+#define	SF_RxDmaStatus		0xf0
+#define	RDS_RxFramesLostCount(x)		((x) & 0xffff)
+
+#define	SF_RxAddressFilteringCtl 0xf4
+#define	RAFC_PerfectAddressPriority(x)		(1U << ((x) + 16))
+#define	RAFC_MinVlanPriority(x)			((x) << 13)
+#define	RAFC_PassMulticastExceptBroadcast	(1U << 12)
+#define	RAFC_WakeupMode(x)			((x) << 10)
+#define	RAFC_VlanMode(x)			((x) << 8)
+#define	RAFC_PerfectFilteringMode(x)		((x) << 6)
+#define	RAFC_HashFilteringMode(x)		((x) << 4)
+#define	RAFC_HashPriorityEnable			(1U << 3)
+#define	RAFC_PassBroadcast			(1U << 2)
+#define	RAFC_PassMulticast			(1U << 1)
+#define	RAFC_PromiscuousMode			(1U << 0)
+
+#define	SF_RxFrameTestOut	0xf8
+
+/*
+ * Additional PCI registers.  To access these registers via I/O space,
+ * indirect access must be used.
+ */
+#define	SF_PciTargetStatus	0x100
+
+#define	SF_PciMasterStatus1	0x104
+
+#define	SF_PciMasterStatus2	0x108
+
+#define	SF_PciDmaLowHostAddr	0x10c
+
+#define	SF_BacDmaDiagnostic0	0x110
+
+#define	SF_BacDmaDiagnostic1	0x114
+
+#define	SF_BacDmaDiagnostic2	0x118
+
+#define	SF_BacDmaDiagnostic3	0x11c
+
+#define	SF_MacAddr1		0x120
+
+#define	SF_MacAddr2		0x124
+
+#define	SF_FunctionEvent	0x130
+
+#define	SF_FunctionEventMask	0x134
+
+#define	SF_FunctionPresentState	0x138
+
+#define	SF_ForceFunction	0x13c
+
+#define	SF_EEPROM_BASE		0x1000
+
+#define	SF_MII_BASE		0x2000
+#define	MiiDataValid		(1U << 31)
+#define	MiiBusy			(1U << 30)
+#define	MiiRegDataPort(x)	((x) & 0xffff)
+
+#define	SF_MII_PHY_REG(p, r)	(SF_MII_BASE +				\
+				 ((p) * 32 * sizeof(uint32_t)) +	\
+				 ((r) * sizeof(uint32_t)))
+
+#define	SF_TestMode		0x4000
+
+#define	SF_RxFrameProcessorCtrl	0x4004
+
+#define	SF_TxFrameProcessorCtrl	0x4008
+
+#define	SF_MacConfig1		0x5000
+#define	MC1_SoftRst			(1U << 15)
+#define	MC1_MiiLoopBack			(1U << 14)
+#define	MC1_TestMode(x)			((x) << 12)
+#define	MC1_TxFlowEn			(1U << 11)
+#define	MC1_RxFlowEn			(1U << 10)
+#define	MC1_PreambleDetectCount		(1U << 9)
+#define	MC1_PassAllRxPackets		(1U << 8)
+#define	MC1_PurePreamble		(1U << 7)
+#define	MC1_LengthCheck			(1U << 6)
+#define	MC1_NoBackoff			(1U << 5)
+#define	MC1_DelayCRC			(1U << 4)
+#define	MC1_TxHalfDuplexJam		(1U << 3)
+#define	MC1_PadEn			(1U << 2)
+#define	MC1_FullDuplex			(1U << 1)
+#define	MC1_HugeFrame			(1U << 0)
+
+#define	SF_MacConfig2		0x5004
+#define	MC2_TxCRCerr			(1U << 15)
+#define	MC2_TxIslCRCerr			(1U << 14)
+#define	MC2_RxCRCerr			(1U << 13)
+#define	MC2_RxIslCRCerr			(1U << 12)
+#define	MC2_TXCF			(1U << 11)
+#define	MC2_CtlSoftRst			(1U << 10)
+#define	MC2_RxSoftRst			(1U << 9)
+#define	MC2_TxSoftRst			(1U << 8)
+#define	MC2_RxISLEn			(1U << 7)
+#define	MC2_BackPressureNoBackOff	(1U << 6)
+#define	MC2_AutoVlanPad			(1U << 5)
+#define	MC2_MandatoryVLANPad		(1U << 4)
+#define	MC2_TxISLAppen			(1U << 3)
+#define	MC2_TxISLEn			(1U << 2)
+#define	MC2_SimuRst			(1U << 1)
+#define	MC2_TxXmtEn			(1U << 0)
+
+#define	SF_BkToBkIPG		0x5008
+
+#define	SF_NonBkToBkIPG		0x500c
+
+#define	SF_ColRetry		0x5010
+
+#define	SF_MaxLength		0x5014
+
+#define	SF_TxNibbleCnt		0x5018
+
+#define	SF_TxByteCnt		0x501c
+
+#define	SF_ReTxCnt		0x5020
+
+#define	SF_RandomNumGen		0x5024
+
+#define	SF_MskRandomNum		0x5028
+
+#define	SF_TotalTxCnt		0x5034
+
+#define	SF_RxByteCnt		0x5040
+
+#define	SF_TxPauseTimer		0x5060
+
+#define	SF_VLANType		0x5064
+
+#define	SF_MiiStatus		0x5070
+
+#define	SF_PERFECT_BASE		0x6000
+#define	SF_PERFECT_SIZE		0x100
+
+#define	SF_HASH_BASE		0x6100
+#define	SF_HASH_SIZE		0x200
+
+#define	SF_STATS_BASE		0x7000
+struct sf_stats {
+	uint32_t	TransmitOKFrames;
+	uint32_t	SingleCollisionFrames;
+	uint32_t	MultipleCollisionFrames;
+	uint32_t	TransmitCRCErrors;
+	uint32_t	TransmitOKOctets;
+	uint32_t	TransmitDeferredFrames;
+	uint32_t	TransmitLateCollisionCount;
+	uint32_t	TransmitPauseControlFrames;
+	uint32_t	TransmitControlFrames;
+	uint32_t	TransmitAbortDueToExcessiveCollisions;
+	uint32_t	TransmitAbortDueToExcessingDeferral;
+	uint32_t	MulticastFramesTransmittedOK;
+	uint32_t	BroadcastFramesTransmittedOK;
+	uint32_t	FramesLostDueToInternalTransmitErrors;
+	uint32_t	ReceiveOKFrames;
+	uint32_t	ReceiveCRCErrors;
+	uint32_t	AlignmentErrors;
+	uint32_t	ReceiveOKOctets;
+	uint32_t	PauseFramesReceivedOK;
+	uint32_t	ControlFramesReceivedOK;
+	uint32_t	ControlFramesReceivedWithUnsupportedOpcode;
+	uint32_t	ReceiveFramesTooLong;
+	uint32_t	ReceiveFramesTooShort;
+	uint32_t	ReceiveFramesJabbersError;
+	uint32_t	ReceiveFramesFragments;
+	uint32_t	ReceivePackets64Bytes;
+	uint32_t	ReceivePackets127Bytes;
+	uint32_t	ReceivePackets255Bytes;
+	uint32_t	ReceivePackets511Bytes;
+	uint32_t	ReceivePackets1023Bytes;
+	uint32_t	ReceivePackets1518Bytes;
+	uint32_t	FramesLostDueToInternalReceiveErrors;
+	uint32_t	TransmitFifoUnderflowCounts;
+};
+
+#define	SF_TxGfpMem		0x8000
+
+#define	SF_RxGfpMem		0xa000
+
+/*
+ * Data structure definitions for the Adaptec AIC-6915 (``Starfire'')
+ * PCI 10/100 Ethernet controller driver.
+ */
+
+/*
+ * Transmit descriptor list size.
+ */
+#define	SF_NTXDESC		256
+#define	SF_NTXDESC_MASK		(SF_NTXDESC - 1)
+#define	SF_NEXTTX(x)		((x + 1) & SF_NTXDESC_MASK)
+
+/*
+ * Transmit completion queue size.  1024 is a hardware requirement.
+ */
+#define	SF_NTCD			1024
+#define	SF_NTCD_MASK		(SF_NTCD - 1)
+#define	SF_NEXTTCD(x)		((x + 1) & SF_NTCD_MASK)
+
+/*
+ * Receive descriptor list size.
+ */
+#define	SF_NRXDESC		256
+#define	SF_NRXDESC_MASK		(SF_NRXDESC - 1)
+#define	SF_NEXTRX(x)		((x + 1) & SF_NRXDESC_MASK)
+
+/*
+ * Receive completion queue size.  1024 is a hardware requirement.
+ */
+#define	SF_NRCD			1024
+#define	SF_NRCD_MASK		(SF_NRCD - 1)
+#define	SF_NEXTRCD(x)		((x + 1) & SF_NRCD_MASK)
+
+/*
+ * Control structures are DMA to the Starfire chip.  We allocate them in
+ * a single clump that maps to a single DMA segment to make several things
+ * easier.
+ */
+struct sf_control_data {
+	/*
+	 * The transmit descriptors.
+	 */
+	struct sf_txdesc0 scd_txdescs[SF_NTXDESC];
+
+	/*
+	 * The transmit completion queue entires.
+	 */
+	struct sf_tcd scd_txcomp[SF_NTCD];
+
+	/*
+	 * The receive buffer descriptors.
+	 */
+	struct sf_rbd32 scd_rxbufdescs[SF_NRXDESC];
+
+	/*
+	 * The receive completion queue entries.
+	 */
+	struct sf_rcd_full scd_rxcomp[SF_NRCD];
+};
+
+#define	SF_CDOFF(x)		offsetof(struct sf_control_data, x)
+#define	SF_CDTXDOFF(x)		SF_CDOFF(scd_txdescs[(x)])
+#define	SF_CDTXCOFF(x)		SF_CDOFF(scd_txcomp[(x)])
+#define	SF_CDRXDOFF(x)		SF_CDOFF(scd_rxbufdescs[(x)])
+#define	SF_CDRXCOFF(x)		SF_CDOFF(scd_rxcomp[(x)])
+
+/*
+ * Software state for transmit and receive descriptors.
+ */
+struct sf_descsoft {
+	struct mbuf *ds_mbuf;		/* head of mbuf chain */
+	bus_dmamap_t ds_dmamap;		/* our DMA map */
+};
+
+/*
+ * Software state per device.
+ */
+struct sf_softc {
+	struct device sc_dev;		/* generic device information */
+	bus_space_tag_t sc_st;		/* bus space tag */
+	bus_space_handle_t sc_sh;	/* bus space handle */
+	bus_space_handle_t sc_sh_func;	/* sub-handle for func regs */
+	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
+	struct arpcom sc_arpcom;	/* ethernet common data */
+	void *sc_sdhook;		/* shutdown hook */
+	int sc_iomapped;		/* are we I/O mapped? */
+
+	struct mii_data sc_mii;		/* MII/media information */
+	struct timeout sc_mii_timeout;	/* MII callout */
+
+	bus_dmamap_t sc_cddmamap;	/* control data DMA map */
+#define	sc_cddma	sc_cddmamap->dm_segs[0].ds_addr
+
+	/*
+	 * Software state for transmit and receive descriptors.
+	 */
+	struct sf_descsoft sc_txsoft[SF_NTXDESC];
+	struct sf_descsoft sc_rxsoft[SF_NRXDESC];
+
+	/*
+	 * Control data structures.
+	 */
+	struct sf_control_data *sc_control_data;
+#define	sc_txdescs	sc_control_data->scd_txdescs
+#define	sc_txcomp	sc_control_data->scd_txcomp
+#define	sc_rxbufdescs	sc_control_data->scd_rxbufdescs
+#define	sc_rxcomp	sc_control_data->scd_rxcomp
+
+	int	sc_txpending;		/* number of Tx requests pending */
+
+	uint32_t sc_InterruptEn;	/* prototype InterruptEn register */
+
+	uint32_t sc_TransmitFrameCSR;	/* prototype TransmitFrameCSR reg */
+	uint32_t sc_TxDescQueueCtrl;	/* prototype TxDescQueueCtrl reg */
+	int	sc_txthresh;		/* current Tx threshold */
+
+	uint32_t sc_MacConfig1;		/* prototype MacConfig1 register */
+
+	uint32_t sc_RxAddressFilteringCtl;
+};
+
+#define	SF_CDTXDADDR(sc, x)	((sc)->sc_cddma + SF_CDTXDOFF((x)))
+#define	SF_CDTXCADDR(sc, x)	((sc)->sc_cddma + SF_CDTXCOFF((x)))
+#define	SF_CDRXDADDR(sc, x)	((sc)->sc_cddma + SF_CDRXDOFF((x)))
+#define	SF_CDRXCADDR(sc, x)	((sc)->sc_cddma + SF_CDRXCOFF((x)))
+
+#define	SF_CDTXDSYNC(sc, x, ops)					\
+	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
+	    SF_CDTXDOFF((x)), sizeof(struct sf_txdesc0), (ops))
+
+#define	SF_CDTXCSYNC(sc, x, ops)					\
+	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
+	    SF_CDTXCOFF((x)), sizeof(struct sf_tcd), (ops))
+
+#define	SF_CDRXDSYNC(sc, x, ops)					\
+	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
+	    SF_CDRXDOFF((x)), sizeof(struct sf_rbd32), (ops))
+
+#define	SF_CDRXCSYNC(sc, x, ops)					\
+	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
+	    SF_CDRXCOFF((x)), sizeof(struct sf_rcd_full), (ops))
+
+#define	SF_INIT_RXDESC(sc, x)						\
+do {									\
+	struct sf_descsoft *__ds = &sc->sc_rxsoft[(x)];			\
+									\
+	(sc)->sc_rxbufdescs[(x)].rbd32_addr =				\
+	    __ds->ds_dmamap->dm_segs[0].ds_addr | RBD_V;		\
+	SF_CDRXDSYNC((sc), (x), BUS_DMASYNC_PREWRITE);			\
+} while (/*CONSTCOND*/0)
+
+#ifdef _KERNEL
+void	sf_attach(struct sf_softc *);
+int	sf_intr(void *);
+#endif /* _KERNEL */
+
+#endif /* _DEV_IC_AIC6915_H_ */