diff options
| author |   kettenis <kettenis@openbsd.org> | 2020-02-20 19:49:15 +0000 |
|---|---|---|
| committer | kettenis <kettenis@openbsd.org> | 2020-02-20 19:49:15 +0000 |
| commit | 2c4a196e661f9bb242c1b5fa748d3cb98a404c8c (patch) | |
| tree | 9f32e8fbace7a18e2880b04e5bd66fbc8fc8b508 /sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c | |
| parent | We do not generate DNS records from text representations. (diff) | |
| download | wireguard-openbsd-2c4a196e661f9bb242c1b5fa748d3cb98a404c8c.tar.xz wireguard-openbsd-2c4a196e661f9bb242c1b5fa748d3cb98a404c8c.zip | |
drm/amd: Add ucode DMCU support
From David Francis
01fcfc83fe07ae42af707c3217f533fb350d4c19 in mainline linux
Diffstat (limited to 'sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c')
| -rw-r--r-- | sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c b/sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c index ae53fa8130a..2bf73f385a8 100644 --- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c +++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c @@ -323,6 +323,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, { const struct common_firmware_header *header = NULL; const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; + const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL; if (NULL == ucode->fw) return 0; @@ -334,8 +335,8 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, return 0; header = (const struct common_firmware_header *)ucode->fw->data; - cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; + dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP || (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 && @@ -344,7 +345,9 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT && ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL && ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM && - ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) { + ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM && + ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM && + ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV)) { ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + @@ -366,6 +369,20 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, le32_to_cpu(header->ucode_array_offset_bytes) + le32_to_cpu(cp_hdr->jt_offset) * 4), ucode->ucode_size); + } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) { + ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - + le32_to_cpu(dmcu_hdr->intv_size_bytes); + + memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + + le32_to_cpu(header->ucode_array_offset_bytes)), + ucode->ucode_size); + } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) { + ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes); + + memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + + le32_to_cpu(header->ucode_array_offset_bytes) + + le32_to_cpu(dmcu_hdr->intv_offset_bytes)), + ucode->ucode_size); } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) { ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl, |