diff options
| author |   jsg <jsg@openbsd.org> | 2020-10-11 05:45:33 +0000 |
|---|---|---|
| committer | jsg <jsg@openbsd.org> | 2020-10-11 05:45:33 +0000 |
| commit | 0f5570612629cd6d43c6720866b77252fc86cd80 (patch) | |
| tree | 8e8b5824f2bdab46f01d885039afe13c735e3504 /sys/dev/pci/drm/include/linux/processor.h | |
| parent | Fix an assert conditioned on DTLS1_VERSION. (diff) | |
| download | wireguard-openbsd-0f5570612629cd6d43c6720866b77252fc86cd80.tar.xz wireguard-openbsd-0f5570612629cd6d43c6720866b77252fc86cd80.zip | |
Align pool items on CACHELINESIZE when replacing linux kmem_cache with
SLAB_HWCACHE_ALIGN flag.
tested by semarie@
Diffstat (limited to 'sys/dev/pci/drm/include/linux/processor.h')
| -rw-r--r-- | sys/dev/pci/drm/include/linux/processor.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/sys/dev/pci/drm/include/linux/processor.h b/sys/dev/pci/drm/include/linux/processor.h index 9ddf8c3a753..9386a526e3c 100644 --- a/sys/dev/pci/drm/include/linux/processor.h +++ b/sys/dev/pci/drm/include/linux/processor.h @@ -19,4 +19,8 @@ cpu_relax(void) } } +#ifndef CACHELINESIZE +#define CACHELINESIZE 64 +#endif + #endif |