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authorkettenis <kettenis@openbsd.org>2021-03-27 20:03:15 +0000
committerkettenis <kettenis@openbsd.org>2021-03-27 20:03:15 +0000
commit9125e0069c7db1eefdb073f443c9bcc88e5de219 (patch)
tree82b7778451a7a598f652779a990dd0a44ac0fd78 /sys/dev/pci/if_ipw.c
parentAdd ARMv8.5 instruction set related CPU features. (diff)
downloadwireguard-openbsd-9125e0069c7db1eefdb073f443c9bcc88e5de219.tar.xz
wireguard-openbsd-9125e0069c7db1eefdb073f443c9bcc88e5de219.zip
Make sure that all CPUs end up with the same bits set in SCTLR_EL1.
Do this by clearing all the bits marked RES0 and set all the bits marked RES1 for the ARMv8.0. Any optional features introduced in later revisions of the architecture (such as PAN) will be enabled after SCTLR_EL1 is initialized. ok patrick@
Diffstat (limited to 'sys/dev/pci/if_ipw.c')
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