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author | 2017-10-11 14:24:12 +0000 | |
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committer | 2017-10-11 14:24:12 +0000 | |
commit | 60fff7d64ed3a656b1dae79e1d4c10e2c1a43115 (patch) | |
tree | bb618e81c85aee3db934995cbcde24ba5c49b472 /sys/dev/usb/files.usb | |
parent | Remove lie talking about splsoftclock(). (diff) | |
download | wireguard-openbsd-60fff7d64ed3a656b1dae79e1d4c10e2c1a43115.tar.xz wireguard-openbsd-60fff7d64ed3a656b1dae79e1d4c10e2c1a43115.zip |
Try to make CPU cache size values more correct, especially on OCTEON II
and III. The logic does not look nice, but the parameters do not follow
the standard config register layout anyway.
Remove unnecessary default values, and assume that the Config1
and Config2 registers are available on every CPU.
Tested on CN5020, CN6120, CN7130 and CN7360.
Diffstat (limited to 'sys/dev/usb/files.usb')
0 files changed, 0 insertions, 0 deletions