diff options
| author |   miod <miod@openbsd.org> | 2005-07-20 21:36:32 +0000 |
|---|---|---|
| committer | miod <miod@openbsd.org> | 2005-07-20 21:36:32 +0000 |
| commit | 30e723d2abc6327dd7d53250b7fb0bd53f8e5958 (patch) | |
| tree | 4fae967d738f2ac1af205e1c2c66bce83aa8619c /sys | |
| parent | add MLINKS for new(ly documented) functions; (diff) | |
| download | wireguard-openbsd-30e723d2abc6327dd7d53250b7fb0bd53f8e5958.tar.xz wireguard-openbsd-30e723d2abc6327dd7d53250b7fb0bd53f8e5958.zip | |
typos
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/mips64/mips64/cache_r10k.S | 4 | ||||
| -rw-r--r-- | sys/arch/mips64/mips64/cache_r5k.S | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/sys/arch/mips64/mips64/cache_r10k.S b/sys/arch/mips64/mips64/cache_r10k.S index bf7a74cbee6..4a402b68286 100644 --- a/sys/arch/mips64/mips64/cache_r10k.S +++ b/sys/arch/mips64/mips64/cache_r10k.S @@ -1,4 +1,4 @@ -/* $OpenBSD: cache_r10k.S,v 1.1 2004/09/20 10:28:36 pefo Exp $ */ +/* $OpenBSD: cache_r10k.S,v 1.2 2005/07/20 21:36:32 miod Exp $ */ /* * Copyright (c) 2004 Opsycon AB (www.opsycon.se) @@ -590,7 +590,7 @@ SyncRD: nop /* - * Sync for aligned read, no writeback requierd. + * Sync for aligned read, no writeback required. */ jal Mips10k_HitInvalidateSCache # L2 cache nop # L1 done in parallel diff --git a/sys/arch/mips64/mips64/cache_r5k.S b/sys/arch/mips64/mips64/cache_r5k.S index 2346e3989a7..87d38aef58a 100644 --- a/sys/arch/mips64/mips64/cache_r5k.S +++ b/sys/arch/mips64/mips64/cache_r5k.S @@ -1,4 +1,4 @@ -/* $OpenBSD: cache_r5k.S,v 1.15 2004/09/29 12:52:44 pefo Exp $ */ +/* $OpenBSD: cache_r5k.S,v 1.16 2005/07/20 21:36:32 miod Exp $ */ /* * Copyright (c) 1998-2004 Opsycon AB (www.opsycon.se) @@ -133,7 +133,7 @@ /* * Due to a flaw in RM7000 1.x processors a pipleine 'drain' is - * requierd after some mtc0 instructions. + * required after some mtc0 instructions. * Ten nops in sequence does the trick. */ #define NOP10 nop;nop;nop;nop;nop;\ @@ -969,7 +969,7 @@ SyncRD: nop /* - * Sync for aligned read, no writeback requierd. + * Sync for aligned read, no writeback required. */ lw t0, CpuCacheType # Aligned, do invalidate and t0, CTYPE_HAS_IL2 # Have internal L2? |