these drivers should have perished in the same fire as mvme88k

discovered by the ever alert mlarkin

3 files changed, 0 insertions, 1179 deletions

diff --git a/sys/dev/ic/mc68681.c b/sys/dev/ic/mc68681.c
deleted file mode 100644
index 884e58e10d0..00000000000
--- a/sys/dev/ic/mc68681.c
+++ /dev/null
@@ -1,833 +0,0 @@
-/*	$OpenBSD: mc68681.c,v 1.3 2013/10/07 17:53:56 miod Exp $	*/
-
-/*
- * Copyright (c) 2013 Miodrag Vallat.
- *
- * Permission to use, copy, modify, and distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-/*
- * Mach Operating System
- * Copyright (c) 1993-1991 Carnegie Mellon University
- * All Rights Reserved.
- *
- * Permission to use, copy, modify and distribute this software and its
- * documentation is hereby granted, provided that both the copyright
- * notice and this permission notice appear in all copies of the
- * software, derivative works or modified versions, and any portions
- * thereof, and that both notices appear in supporting documentation.
- *
- * CARNEGIE MELLON AND OMRON ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS IS"
- * CONDITION.  CARNEGIE MELLON AND OMRON DISCLAIM ANY LIABILITY OF ANY KIND
- * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- *
- * Carnegie Mellon requests users of this software to return to
- *
- *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
- *  School of Computer Science
- *  Carnegie Mellon University
- *  Pittsburgh PA 15213-3890
- *
- * any improvements or extensions that they make and grant Carnegie the
- * rights to redistribute these changes.
- */
-
-#include <sys/param.h>
-#include <sys/ioctl.h>
-#include <sys/proc.h>
-#include <sys/tty.h>
-#include <sys/systm.h>
-#include <sys/conf.h>
-#include <sys/device.h>
-
-#include <dev/ic/mc68681reg.h>
-#include <dev/ic/mc68681var.h>
-
-#ifdef	DDB
-#include <ddb/db_var.h>
-#endif
-
-#define	DART_UNIT(dev)	(minor(dev) / N68681PORTS)
-#define DART_PORT(dev)	(minor(dev) % N68681PORTS)
-
-struct cfdriver dart_cd = {
-	NULL, "dart", DV_TTY
-};
-
-#define	MC68681_A_BASE	0x00
-#define	MC68681_B_BASE	0x08
-
-cdev_decl(dart);
-
-void	mc68681_set_acr(struct mc68681_softc *);
-const struct mc68681_s *mc68681_speed(int);
-void	mc68681_start(struct tty *);
-int	mc68681_mctl(struct mc68681_softc *, int, int, int);
-int	mc68681_param(struct tty *, struct termios *);
-void	mc68681_dcdint(struct mc68681_softc *);
-void	mc68681_rxint(struct mc68681_softc *, int);
-void	mc68681_txint(struct mc68681_softc *, int);
-
-void
-mc68681_common_attach(struct mc68681_softc *sc)
-{
-	sc->sc_line[A_PORT].speed = sc->sc_line[B_PORT].speed =
-	    mc68681_speed(B9600);
-
-	sc->sc_sw_reg->mr1[A_PORT] = sc->sc_sw_reg->mr1[B_PORT] =
-	    DART_MR1_RX_IRQ_RXRDY | DART_MR1_ERROR_CHAR |
-	    DART_MR1_PARITY_NONE | DART_MR1_RX_RTR | DART_MR1_BPC_8;
-	sc->sc_sw_reg->mr2[A_PORT] = sc->sc_sw_reg->mr2[B_PORT] =
-	    DART_MR2_MODE_NORMAL | /* DART_MR2_TX_CTS | */ DART_MR2_STOP_1;
-	sc->sc_sw_reg->cr[A_PORT] = sc->sc_sw_reg->cr[B_PORT] =
-	    DART_CR_TX_ENABLE | DART_CR_RX_ENABLE;
-
-	sc->sc_sw_reg->acr &= ~DART_ACR_BRG_SET_MASK;
-	sc->sc_sw_reg->acr |= DART_ACR_BRG_SET_2;
-
-	/* Start out with Tx and RX interrupts disabled, but enable input port
-	   change interrupt */
-	sc->sc_sw_reg->imr |= DART_ISR_IP_CHANGE;
-
-	if (sc->sc_consport >= 0) {
-		printf(": console");
-		delay(10000);
-	}
-
-	mc68681_set_acr(sc);
-
-	(*sc->sc_write)(sc, DART_IMR, sc->sc_sw_reg->imr);
-
-	printf("\n");
-}
-
-/*
- * Update the ACR register. This requires both ports to be disabled.
- * Restart timer if necessary.
- */
-void
-mc68681_set_acr(struct mc68681_softc *sc)
-{
-	uint8_t acr;
-
-	acr = sc->sc_sw_reg->acr;
-	/*
-	 * If MD attachment configures a timer, ignore this until the timer
-	 * limit has been correctly set up. This allows this function to be
-	 * invoked at attach time, before cpu_initclocks() gets a chance to
-	 * run.
-	 */
-	if (ISSET(acr, DART_ACR_CT_TIMER_BIT) && *sc->sc_sw_reg->ct == 0)
-		acr = (acr & ~DART_ACR_CT_MASK) | DART_ACR_CT_COUNTER_CLK_16;
-
-	/* reset port a */
-	(*sc->sc_write)(sc, DART_CRA,
-	    DART_CR_RESET_RX | DART_CR_TX_DISABLE | DART_CR_RX_DISABLE);
-	(*sc->sc_write)(sc, DART_CRA,
-	    DART_CR_RESET_TX /* | DART_CR_TX_DISABLE | DART_CR_RX_DISABLE */);
-	(*sc->sc_write)(sc, DART_CRA,
-	    DART_CR_RESET_ERROR /* | DART_CR_TX_DISABLE | DART_CR_RX_DISABLE */);
-	(*sc->sc_write)(sc, DART_CRA,
-	    DART_CR_RESET_BREAK /* | DART_CR_TX_DISABLE | DART_CR_RX_DISABLE */);
-	(*sc->sc_write)(sc, DART_CRA,
-	    DART_CR_RESET_MR1 /* | DART_CR_TX_DISABLE | DART_CR_RX_DISABLE */);
-
-	/* reset port b */
-	(*sc->sc_write)(sc, DART_CRB,
-	    DART_CR_RESET_RX | DART_CR_TX_DISABLE | DART_CR_RX_DISABLE);
-	(*sc->sc_write)(sc, DART_CRB,
-	    DART_CR_RESET_TX /* | DART_CR_TX_DISABLE | DART_CR_RX_DISABLE */);
-	(*sc->sc_write)(sc, DART_CRB,
-	    DART_CR_RESET_ERROR /* | DART_CR_TX_DISABLE | DART_CR_RX_DISABLE */);
-	(*sc->sc_write)(sc, DART_CRB,
-	    DART_CR_RESET_BREAK /* | DART_CR_TX_DISABLE | DART_CR_RX_DISABLE */);
-	(*sc->sc_write)(sc, DART_CRB,
-	    DART_CR_RESET_MR1 /* | DART_CR_TX_DISABLE | DART_CR_RX_DISABLE */);
-
-	(*sc->sc_write)(sc, DART_OPRS, sc->sc_sw_reg->oprs);
-	(*sc->sc_write)(sc, DART_OPCR, sc->sc_sw_reg->opcr);
-
-	(*sc->sc_write)(sc, DART_ACR, acr);
-	/*
-	 * Restart timer if necessary.
-	 * XXX This loses the current timer cycle.
-	 */
-	if (ISSET(acr, DART_ACR_CT_TIMER_BIT)) {
-		(*sc->sc_write)(sc, DART_CTUR, *sc->sc_sw_reg->ct >> 8);
-		(*sc->sc_write)(sc, DART_CTLR, *sc->sc_sw_reg->ct & 0xff);
-		(*sc->sc_read)(sc, DART_CTSTART);
-	}
-
-	/* reinitialize ports */
-	(*sc->sc_write)(sc, DART_MRA, sc->sc_sw_reg->mr1[A_PORT]);
-	(*sc->sc_write)(sc, DART_MRA, sc->sc_sw_reg->mr2[A_PORT]);
-	(*sc->sc_write)(sc, DART_CSRA, sc->sc_line[A_PORT].speed->csr);
-	(*sc->sc_write)(sc, DART_CRA, sc->sc_sw_reg->cr[A_PORT]);
-
-	(*sc->sc_write)(sc, DART_MRB, sc->sc_sw_reg->mr1[B_PORT]);
-	(*sc->sc_write)(sc, DART_MRB, sc->sc_sw_reg->mr2[B_PORT]);
-	(*sc->sc_write)(sc, DART_CSRB, sc->sc_line[B_PORT].speed->csr);
-	(*sc->sc_write)(sc, DART_CRB, sc->sc_sw_reg->cr[B_PORT]);
-}
-
-/* speed table */
-static const struct mc68681_s mc68681_speeds[] = {
-#define	MC68681_SPEED(spd,sets) \
-	{ .speed = spd, .brg_sets = sets, \
-	  .csr = (DART_CSR_##spd << DART_CSR_RXCLOCK_SHIFT) | \
-	         (DART_CSR_##spd << DART_CSR_TXCLOCK_SHIFT) }
-	MC68681_SPEED(50, 1),
-	MC68681_SPEED(75, 2),
-	MC68681_SPEED(110, 1 | 2),
-	MC68681_SPEED(134, 1 | 2),
-	MC68681_SPEED(150, 2),
-	MC68681_SPEED(200, 1),
-	MC68681_SPEED(300, 1 | 2),
-	MC68681_SPEED(600, 1 | 2),
-	MC68681_SPEED(1050, 1),
-	MC68681_SPEED(1200, 1 | 2),
-	MC68681_SPEED(1800, 2),
-	MC68681_SPEED(2000, 2),
-	MC68681_SPEED(2400, 1 | 2),
-	MC68681_SPEED(4800, 1 | 2),
-	MC68681_SPEED(7200, 1),
-	MC68681_SPEED(9600, 1 | 2),
-	MC68681_SPEED(19200, 2),
-	MC68681_SPEED(38400, 1)
-#undef MC68681_SPEED
-};
-
-const struct mc68681_s *
-mc68681_speed(int speed)
-{
-	const struct mc68681_s *mcs;
-	uint n;
-
-	for (n = nitems(mc68681_speeds), mcs = mc68681_speeds; n != 0;
-	    n--, mcs++) {
-		if (mcs->speed == speed)
-			return mcs;
-	}
-
-	return NULL;
-}
-
-void
-mc68681_start(struct tty *tp)
-{
-	struct mc68681_softc *sc;
-	dev_t dev;
-	int s;
-	int port, tries;
-	int c;
-	uint ptaddr;
-	uint8_t imrbit;
-
-	if ((tp->t_state & TS_ISOPEN) == 0)
-		return;
-
-	dev = tp->t_dev;
-	sc = (struct mc68681_softc *)dart_cd.cd_devs[DART_UNIT(dev)];
-	port = DART_PORT(dev);
-	ptaddr = port ? MC68681_B_BASE : MC68681_A_BASE;
-	imrbit = port ? DART_ISR_TXB : DART_ISR_TXA;
-
-	s = spltty();
-
-	if (tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP))
-		goto bail;
-
-	ttwakeupwr(tp);
-	if (tp->t_outq.c_cc == 0)
-		goto bail;
-
-	tp->t_state |= TS_BUSY;
-	while (tp->t_outq.c_cc != 0) {
-		/* load transmitter until it is full */
-		for (tries = 10000; tries != 0; tries --)
-			if ((*sc->sc_read)(sc, ptaddr + DART_SRA) &
-			    DART_SR_TX_READY)
-				break;
-
-		if (tries == 0) {
-			if (!ISSET(sc->sc_sw_reg->imr, imrbit)) {
-				sc->sc_sw_reg->imr |= imrbit;
-				(*sc->sc_write)(sc, DART_IMR, sc->sc_sw_reg->imr);
-			}
-			goto bail;
-		}
-
-		c = getc(&tp->t_outq);
-		(*sc->sc_write)(sc, ptaddr + DART_TBA, c & 0xff);
-	}
-	tp->t_state &= ~TS_BUSY;
-
-bail:
-	splx(s);
-}
-
-int
-dartstop(struct tty *tp, int flag)
-{
-	int s;
-
-	s = spltty();
-	if (tp->t_state & TS_BUSY) {
-		if ((tp->t_state & TS_TTSTOP) == 0)
-			tp->t_state |= TS_FLUSH;
-	}
-	splx(s);
-
-	return 0;
-}
-
-/*
- * To be called at spltty - tty already locked.
- * Returns status of carrier.
- */
-
-int
-mc68681_mctl(struct mc68681_softc *sc, int port, int flags, int how)
-{
-	int op, newflags = 0;
-	struct mc68681_line *line;
-	int s;
-
-	line = &sc->sc_line[port];
-
-	s = spltty();
-
-	if (flags & TIOCM_DTR) {
-		op = sc->sc_hw[port].dtr_op;
-		if (op >= 0) {
-			newflags |= 1 << op;
-			flags &= ~TIOCM_DTR;
-		}
-	}
-	if (flags & TIOCM_RTS) {
-		op = sc->sc_hw[port].rts_op;
-		if (op >= 0) {
-			newflags |= 1 << op;
-			flags &= ~TIOCM_RTS;
-		}
-	}
-
-	switch (how) {
-	case DMSET:
-		(*sc->sc_write)(sc, DART_OPRS, newflags);
-		(*sc->sc_write)(sc, DART_OPRR, ~newflags);
-		break;
-	case DMBIS:
-		(*sc->sc_write)(sc, DART_OPRS, newflags);
-		break;
-	case DMBIC:
-		(*sc->sc_write)(sc, DART_OPRR, newflags);
-		break;
-	case DMGET:
-		flags = 0;	/* XXX not supported */
-		break;
-	}
-
-	splx(s);
-	return flags;
-}
-
-int
-dartioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
-{
-	int error;
-	int unit, port;
-	struct tty *tp;
-	struct mc68681_line *line;
-	struct mc68681_softc *sc;
-
-	unit = DART_UNIT(dev);
-	if (unit >= dart_cd.cd_ndevs)
-		return ENXIO;
-	sc = (struct mc68681_softc *)dart_cd.cd_devs[unit];
-	if (sc == NULL)
-		return ENXIO;
-	port = DART_PORT(dev);
-	line = &sc->sc_line[port];
-	tp = line->tty;
-
-	error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
-	if (error >= 0)
-		return error;
-
-	error = ttioctl(tp, cmd, data, flag, p);
-	if (error >= 0)
-		return error;
-
-	switch (cmd) {
-	case TIOCSBRK:
-	case TIOCCBRK:
-		break;
-	case TIOCSDTR:
-		(void)mc68681_mctl(sc, port, TIOCM_DTR | TIOCM_RTS, DMBIS);
-		break;
-	case TIOCCDTR:
-		(void)mc68681_mctl(sc, port, TIOCM_DTR | TIOCM_RTS, DMBIC);
-		break;
-	case TIOCMSET:
-		(void)mc68681_mctl(sc, port, *(int *)data, DMSET);
-		break;
-	case TIOCMBIS:
-		(void)mc68681_mctl(sc, port, *(int *)data, DMBIS);
-		break;
-	case TIOCMBIC:
-		(void)mc68681_mctl(sc, port, *(int *)data, DMBIC);
-		break;
-	case TIOCMGET:
-		*(int *)data = mc68681_mctl(sc, port, 0, DMGET);
-		break;
-	case TIOCGFLAGS:
-		if (sc->sc_consport == port)
-			line->swflags |= TIOCFLAG_SOFTCAR;
-		*(int *)data = line->swflags;
-		break;
-	case TIOCSFLAGS:
-		error = suser(p, 0);
-		if (error != 0)
-			return EPERM;
-
-		line->swflags = *(int *)data;
-		if (sc->sc_consport == port)
-			line->swflags |= TIOCFLAG_SOFTCAR;
-		line->swflags &= /* only allow valid flags */
-		    (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | TIOCFLAG_CRTSCTS);
-		break;
-	default:
-		return ENOTTY;
-	}
-
-	return 0;
-}
-
-int
-mc68681_param(struct tty *tp, struct termios *t)
-{
-	int unit, port, s, acrupdate;
-	const struct mc68681_s *spd;
-	uint8_t acr, mr1, mr2;
-	struct mc68681_line *line;
-	struct mc68681_softc *sc;
-	dev_t dev;
-	uint ptaddr;
-
-	dev = tp->t_dev;
-	unit = DART_UNIT(dev);
-	sc = (struct mc68681_softc *)dart_cd.cd_devs[unit];
-	port = DART_PORT(dev);
-	line = &sc->sc_line[port];
-	ptaddr = port ? MC68681_B_BASE : MC68681_A_BASE;
-
-	tp->t_ispeed = t->c_ispeed;
-	tp->t_ospeed = t->c_ospeed;
-	tp->t_cflag = t->c_cflag;
-
-	/* Reset to make global changes */
-	if (sc->sc_consport != port) {
-		/* disable Tx and Rx */
-		if (port == A_PORT)
-			sc->sc_sw_reg->imr &= ~(DART_ISR_TXA | DART_ISR_RXA);
-		else
-			sc->sc_sw_reg->imr &= ~(DART_ISR_TXB | DART_ISR_RXB);
-		(*sc->sc_write)(sc, DART_IMR, sc->sc_sw_reg->imr);
-
-		acrupdate = 0;
-
-		/*
-		 * Try to set baudrate. If the rate being asked for
-		 * uses a different BRG than the other port, bail
-		 * out with EAGAIN.
-		 * Note that, upon close, we will reset to 9600
-		 * bps which is compatible with both BRG.
-		 */
-		spd = mc68681_speed(tp->t_ispeed);
-		if (spd == NULL)
-			return EINVAL;
-		if ((spd->brg_sets &
-		    sc->sc_line[port ^ 1].speed->brg_sets) == 0)
-			return EAGAIN;
-		line->speed = spd;
-		if (spd->brg_sets != (1 | 2)) {
-			acr = sc->sc_sw_reg->acr;
-			switch (acr & DART_ACR_BRG_SET_MASK) {
-			case DART_ACR_BRG_SET_2:
-				if (spd->brg_sets == 1) {
-					acr &= ~DART_ACR_BRG_SET_MASK;
-					acr |= DART_ACR_BRG_SET_1;
-				}
-				break;
-			case DART_ACR_BRG_SET_1:
-				if (spd->brg_sets == 2) {
-					acr &= ~DART_ACR_BRG_SET_MASK;
-					acr |= DART_ACR_BRG_SET_2;
-				}
-				break;
-			}
-			if (acr != sc->sc_sw_reg->acr) {
-				sc->sc_sw_reg->acr = acr;
-				acrupdate = 1;
-			}
-		}
-		if (acrupdate == 0)
-			(*sc->sc_write)(sc, ptaddr + DART_CSRA, spd->csr);
-
-		/* get saved mode registers and clear set up parameters */
-		mr1 = sc->sc_sw_reg->mr1[port];
-		mr1 &= ~(DART_MR1_BPC_MASK | DART_MR1_PARITY_MASK);
-		mr2 = sc->sc_sw_reg->mr2[port];
-		mr2 &= ~DART_MR2_STOP_MASK;
-
-		/* set up character size */
-		switch (t->c_cflag & CSIZE) {
-		case CS8:
-			mr1 |= DART_MR1_BPC_8;
-			break;
-		case CS7:
-			mr1 |= DART_MR1_BPC_7;
-			break;
-		case CS6:
-			mr1 |= DART_MR1_BPC_6;
-			break;
-		case CS5:
-			mr1 |= DART_MR1_BPC_5;
-			break;
-		}
-
-		/* set up stop bits */
-		if (t->c_cflag & CSTOPB)
-			mr2 |= DART_MR2_STOP_2;
-		else {
-			/*
-			 * When running in 5 bpc mode, low stop bit length
-			 * values are actually off .5 stop bits.
-			 */
-			if ((t->c_cflag & CSIZE) == CS5)
-				mr2 |= DART_MR2_STOP_1_CL5;
-			else
-				mr2 |= DART_MR2_STOP_1;
-		}
-
-		/* set up parity */
-		if (t->c_cflag & PARENB) {
-			mr1 |= DART_MR1_PARITY_ENABLE;
-			if (t->c_cflag & PARODD)
-				mr1 |= DART_MR1_PARITY_ENABLE_ODD;
-			else
-				mr1 |= DART_MR1_PARITY_ENABLE_EVEN;
-		} else
-			mr1 |= DART_MR1_PARITY_NONE;
-
-		if (sc->sc_sw_reg->mr1[port] != mr1 ||
-		    sc->sc_sw_reg->mr2[port] != mr2) {
-			if (acrupdate == 0) {
-				/* write mode registers to duart */
-				(*sc->sc_write)(sc, ptaddr + DART_CRA,
-				    DART_CR_RESET_MR1);
-				(*sc->sc_write)(sc, ptaddr + DART_MRA, mr1);
-				(*sc->sc_write)(sc, ptaddr + DART_MRA, mr2);
-			}
-
-			/* save changed mode registers */
-			sc->sc_sw_reg->mr1[port] = mr1;
-			sc->sc_sw_reg->mr2[port] = mr2;
-		}
-
-		if (acrupdate != 0) {
-			s = spltty();
-			mc68681_set_acr(sc);
-			splx(s);
-		}
-	}
-
-	/* enable transmitter? */
-	if (tp->t_state & TS_BUSY) {
-		if (port == A_PORT)
-			sc->sc_sw_reg->imr |= DART_ISR_TXA;
-		else
-			sc->sc_sw_reg->imr |= DART_ISR_TXB;
-		/* will be done below
-		(*sc->sc_write)(sc, DART_IMR, sc->sc_sw_reg->imr); */
-	}
-
-	/* re-enable the receiver */
-	if (port == A_PORT)
-		sc->sc_sw_reg->imr |= DART_ISR_RXA;
-	else
-		sc->sc_sw_reg->imr |= DART_ISR_RXB;
-	(*sc->sc_write)(sc, DART_IMR, sc->sc_sw_reg->imr);
-
-	return 0;
-}
-
-void
-mc68681_dcdint(struct mc68681_softc *sc)
-{
-	unsigned int dcdstate;
-	uint8_t ipcr, ip, ip_bit;
-	struct tty *tp;
-	int port;
-	struct mc68681_line *line;
-
-	ipcr = (*sc->sc_read)(sc, DART_IPCR);
-	ip = (*sc->sc_read)(sc, DART_IP);
-
-	for (port = A_PORT; port <= B_PORT; port++) {
-		ip_bit = 0;
-		switch (sc->sc_hw[port].dcd_ip) {
-		case 3:
-			if (ipcr & DART_IPCR_IP3_CHANGED)
-				ip_bit = DART_IP_IP3;
-			break;
-		case 2:
-			if (ipcr & DART_IPCR_IP2_CHANGED)
-				ip_bit = DART_IP_IP2;
-			break;
-		case 1:
-			if (ipcr & DART_IPCR_IP1_CHANGED)
-				ip_bit = DART_IP_IP1;
-			break;
-		case 0:
-			if (ipcr & DART_IPCR_IP0_CHANGED)
-				ip_bit = DART_IP_IP0;
-			break;
-		}
-
-		if (ip_bit != 0) {
-			dcdstate = ip & ip_bit;
-			if (sc->sc_hw[port].dcd_active_low)
-				dcdstate = !dcdstate;
-
-			line = &sc->sc_line[port];
-			tp = line->tty;
-			if (tp != NULL)
-				(*linesw[tp->t_line].l_modem)(tp, dcdstate);
-		}
-	}
-}
-
-struct tty *
-darttty(dev_t dev)
-{
-	int unit, port;
-	struct mc68681_softc *sc;
-
-	unit = DART_UNIT(dev);
-	sc = (struct mc68681_softc *)dart_cd.cd_devs[unit];
-	port = DART_PORT(dev);
-	return sc->sc_line[port].tty;
-}
-
-int
-dartopen(dev_t dev, int flag, int mode, struct proc *p)
-{
-	int s, unit, port;
-	struct mc68681_line *line;
-	struct mc68681_softc *sc;
-	struct tty *tp;
-
-	unit = DART_UNIT(dev);
-	if (unit >= dart_cd.cd_ndevs)
-		return ENXIO;
-	sc = (struct mc68681_softc *)dart_cd.cd_devs[unit];
-	if (sc == NULL)
-		return ENXIO;
-	port = DART_PORT(dev);
-	line = &sc->sc_line[port];
-
-	s = spltty();
-	if (line->tty != NULL)
-		tp = line->tty;
-	else
-		tp = line->tty = ttymalloc(0);
-
-	tp->t_oproc = mc68681_start;
-	tp->t_param = mc68681_param;
-	tp->t_dev = dev;
-
-	if ((tp->t_state & TS_ISOPEN) == 0) {
-		ttychars(tp);
-		tp->t_iflag = TTYDEF_IFLAG;
-		tp->t_oflag = TTYDEF_OFLAG;
-		tp->t_lflag = TTYDEF_LFLAG;
-		tp->t_ispeed = tp->t_ospeed = B9600;
-		mc68681_param(tp, &tp->t_termios);
-		if (sc->sc_consport == port) {
-			/* console is 8N1 */
-			tp->t_cflag = CREAD | CS8 | HUPCL;
-		} else {
-			tp->t_cflag = TTYDEF_CFLAG;
-		}
-		ttsetwater(tp);
-		(void)mc68681_mctl(sc, port, TIOCM_DTR | TIOCM_RTS, DMSET);
-		tp->t_state |= TS_CARR_ON;
-	} else if (tp->t_state & TS_XCLUDE && suser(p, 0) != 0) {
-		splx(s);
-		return EBUSY;
-	}
-
-	splx(s);
-	return (*linesw[tp->t_line].l_open)(dev, tp, p);
-}
-
-int
-dartclose(dev_t dev, int flag, int mode, struct proc *p)
-{
-	struct tty *tp;
-	struct mc68681_line *line;
-	struct mc68681_softc *sc;
-
-	sc = (struct mc68681_softc *)dart_cd.cd_devs[DART_UNIT(dev)];
-	line = &sc->sc_line[DART_PORT(dev)];
-	tp = line->tty;
-
-	(*linesw[tp->t_line].l_close)(tp, flag, p);
-	ttyclose(tp);
-
-	return 0;
-}
-
-int
-dartread(dev_t dev, struct uio *uio, int flag)
-{
-	struct tty *tp;
-	struct mc68681_softc *sc;
-
-	sc = (struct mc68681_softc *)dart_cd.cd_devs[DART_UNIT(dev)];
-	tp = sc->sc_line[DART_PORT(dev)].tty;
-
-	return (*linesw[tp->t_line].l_read)(tp, uio, flag);
-}
-
-int
-dartwrite(dev_t dev, struct uio *uio, int flag)
-{
-	struct tty *tp;
-	struct mc68681_softc *sc;
-
-	sc = (struct mc68681_softc *)dart_cd.cd_devs[DART_UNIT(dev)];
-	tp = sc->sc_line[DART_PORT(dev)].tty;
-
-	return (*linesw[tp->t_line].l_write)(tp, uio, flag);
-}
-
-void
-mc68681_rxint(struct mc68681_softc *sc, int port)
-{
-	struct tty *tp;
-	uint8_t data, sr;
-	uint ptaddr;
-
-	tp = sc->sc_line[port].tty;
-	ptaddr = port ? MC68681_B_BASE : MC68681_A_BASE;
-
-	/* read status reg */
-	while ((sr = (*sc->sc_read)(sc, ptaddr + DART_SRA)) &
-	    DART_SR_RX_READY) {
-		/* read data and reset receiver */
-		data = (*sc->sc_read)(sc, ptaddr + DART_RBA);
-
-		if ((tp->t_state & (TS_ISOPEN|TS_WOPEN)) == 0 &&
-		    sc->sc_consport != port) {
-			return;
-		}
-
-		if (sr & DART_SR_BREAK) {
-			/* clear break state */
-			(*sc->sc_write)(sc, ptaddr + DART_CRA,
-			    DART_CR_RESET_BREAK);
-			(*sc->sc_write)(sc, ptaddr + DART_CRA,
-			    DART_CR_RESET_ERROR);
-
-#if defined(DDB)
-			if (db_console != 0 && sc->sc_consport == port)
-				Debugger();
-#endif
-		} else if (sr & (DART_SR_FRAME | DART_SR_PARITY |
-		    DART_SR_OVERRUN)) { /* errors */
-			if (sr & DART_SR_OVERRUN)
-				printf("%s: receiver overrun port %c\n",
-				    sc->sc_dev.dv_xname, 'A' + port);
-			if (sr & DART_SR_FRAME)
-				printf("%s: framing error port %c\n",
-				    sc->sc_dev.dv_xname, 'A' + port);
-			if (sr & DART_SR_PARITY)
-				printf("%s: parity error port %c\n",
-				    sc->sc_dev.dv_xname, 'A' + port);
-			/* clear error state */
-			(*sc->sc_write)(sc, ptaddr + DART_CRA,
-			    DART_CR_RESET_ERROR);
-		} else {
-			/* no errors */
-			if (ISSET(tp->t_state, TS_ISOPEN))
-				(*linesw[tp->t_line].l_rint)(data,tp);
-		}
-	}
-}
-
-void
-mc68681_txint(struct mc68681_softc *sc, int port)
-{
-	struct tty *tp;
-
-	tp = sc->sc_line[port].tty;
-
-	if ((tp->t_state & (TS_ISOPEN|TS_WOPEN))==0)
-		goto out;
-
-	if (tp->t_state & TS_FLUSH)
-		tp->t_state &= ~TS_FLUSH;
-
-	if (tp->t_state & TS_BUSY) {
-		tp->t_state &= ~TS_BUSY;
-		(*linesw[tp->t_line].l_start)(tp);
-		if (tp->t_state & TS_BUSY) {
-			return;
-		}
-	}
-out:
-
-	/* disable transmitter */
-	if (port == A_PORT)
-		sc->sc_sw_reg->imr &= ~DART_ISR_TXA;
-	else
-		sc->sc_sw_reg->imr &= ~DART_ISR_TXB;
-
-	(*sc->sc_write)(sc, DART_IMR, sc->sc_sw_reg->imr);
-}
-
-void
-mc68681_intr(struct mc68681_softc *sc, uint8_t isr)
-{
-	if (isr & DART_ISR_IP_CHANGE)
-		mc68681_dcdint(sc);
-
-	if (isr & DART_ISR_RXA)
-		mc68681_rxint(sc, A_PORT);
-	if (isr & DART_ISR_RXB)
-		mc68681_rxint(sc, B_PORT);
-
-	if (isr & DART_ISR_TXA)
-		mc68681_txint(sc, A_PORT);
-	if (isr & DART_ISR_TXB)
-		mc68681_txint(sc, B_PORT);
-
-#if 0 /* not enabled in imr */
-	if (isr & DART_ISR_DELTA_BREAK_A)
-		(*sc->sc_write)(sc, DART_CRA, DART_CR_RESET_BREAK);
-	if (isr & DART_ISR_DELTA_BREAK_B)
-		(*sc->sc_write)(sc, DART_CRB, DART_CR_RESET_BREAK);
-#endif
-}
diff --git a/sys/dev/ic/mc68681reg.h b/sys/dev/ic/mc68681reg.h
deleted file mode 100644
index 2b29ede7407..00000000000
--- a/sys/dev/ic/mc68681reg.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/*	$OpenBSD: mc68681reg.h,v 1.1 2013/06/11 21:03:39 miod Exp $	*/
-
-/*
- * Copyright (c) 2013 Miodrag Vallat.
- *
- * Permission to use, copy, modify, and distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * MC68HC681 Dual Asynchronous Receiver/Transmitter registers
- */
-
-/*
- * Register Addresses
- */
-
-#define	DART_MRA	0x00	/* Mode Register A (rw) */
-#define	DART_SRA	0x01	/* Status Register A (r) */
-#define	DART_CSRA	0x01	/* Clock-Select Register A (w) */
-#define	DART_CRA	0x02	/* Command Register A (w) */
-#define	DART_RBA	0x03	/* Receiver Buffer A (r) */
-#define	DART_TBA	0x03	/* Transmitter Buffer A (w) */
-#define	DART_IPCR	0x04	/* Input Port Change Register (r) */
-#define	DART_ACR	0x04	/* Auxiliary Control Register (w) */
-#define	DART_ISR	0x05	/* Interrupt Status Register (r) */
-#define	DART_IMR	0x05	/* Interrupt Mask Register (w) */
-#define	DART_CUR	0x06	/* Counter Mode Current MSB (r) */
-#define	DART_CTUR	0x06	/* Counter/Timer Upper Register (w) */
-#define	DART_CLR	0x07	/* Counter Mode Current LSB (r) */
-#define	DART_CTLR	0x07	/* Counter/Timer Lower Register (w) */
-#define	DART_MRB	0x08	/* Mode Register B (rw) */
-#define	DART_SRB	0x09	/* Status Register B (r) */
-#define	DART_CSRB	0x09	/* Clock-Select Register B (w) */
-#define	DART_CRB	0x0a	/* Command Register B (w) */
-#define	DART_RBB	0x0b	/* Receiver Buffer B (r) */
-#define	DART_TBB	0x0b	/* Transmitter Buffer B (w) */
-#define	DART_IVR	0x0c	/* Interrupt-Vector Register (rw) */
-#define	DART_IP		0x0d	/* Input Port (r) */
-#define	DART_OPCR	0x0d	/* Output Port Configuration Register (w) */
-#define	DART_CTSTART	0x0e	/* Start-Counter Command (r) */
-#define	DART_OPRS	0x0e	/* Output Port Bit Set Command (w) */
-#define	DART_CTSTOP	0x0f	/* Stop-Counter Command (r) */
-#define	DART_OPRR	0x0f	/* Output Port Bit Reset Command (w) */
-
-#define	DART_SIZE	0x10
-
-/*
- * Mode Register 1
- */
-
-#define	DART_MR1_RX_RTR			0x80	/* OP0 set on RX RTR */
-#define	DART_MR1_RX_IRQ_FFULL		0x40	/* RX interrupt on FIFO full */
-#define	DART_MR1_RX_IRQ_RXRDY		0x00	/* RX interrupt on RxRDY */
-#define	DART_MR1_ERROR_BLOCK		0x20	/* whole RX FIFO status */
-#define	DART_MR1_ERROR_CHAR		0x00
-#define	DART_MR1_PARITY_MASK		0x1c
-#define	DART_MR1_PARITY_MULTI		0x18	/* multidrop mode */
-#define	DART_MR1_PARITY_NONE		0x10	/* no parity */
-#define	DART_MR1_PARITY_FORCED		0x08
-#define	DART_MR1_PARITY_ENABLE		0x00
-#define	DART_MR1_MULTIDROP_ADDRESS	0x04
-#define	DART_MR1_MULTIDROP_DATA		0x00
-#define	DART_MR1_PARITY_FORCED_HIGH	0x04
-#define	DART_MR1_PARITY_FORCED_LOW	0x00
-#define	DART_MR1_PARITY_ENABLE_ODD	0x04
-#define	DART_MR1_PARITY_ENABLE_EVEN	0x00
-#define	DART_MR1_BPC_MASK		0x03
-#define	DART_MR1_BPC_8			0x03
-#define	DART_MR1_BPC_7			0x02
-#define	DART_MR1_BPC_6			0x01
-#define	DART_MR1_BPC_5			0x00
-
-/*
- * Mode Register 2
- */
-
-#define	DART_MR2_MODE_MASK		0xc0
-#define	DART_MR2_MODE_REMOTE_LOOPBACK	0xc0
-#define	DART_MR2_MODE_LOCAL_LOOPBACK	0x80
-#define	DART_MR2_MODE_ECHO		0x40
-#define	DART_MR2_MODE_NORMAL		0x00
-#define	DART_MR2_TX_RTS			0x20	/* OP0 reset on TX RTS */
-#define	DART_MR2_TX_CTS			0x10	/* IP0 controls TX CTS */
-#if 0 /* 68681 datasheet values */
-#define	DART_MR2_STOP_MASK		0x0c
-#define	DART_MR2_STOP_2			0x0c
-#define	DART_MR2_STOP_15		0x08	/* 1.5 if async, 2 if sync */
-#define	DART_MR2_STOP_1			0x04
-#else /* 68692 datasheet values */
-#define	DART_MR2_STOP_MASK		0x0f
-#define	DART_MR2_STOP_2			0x0f
-#define	DART_MR2_STOP_15		0x08	/* 1.5 if async, 2 if sync */
-#define	DART_MR2_STOP_1			0x07
-#define	DART_MR2_STOP_15_CL5		0x07
-#define	DART_MR2_STOP_1_CL5		0x00
-#endif
-
-/*
- * Clock-Select Register
- */
-
-#define	DART_CSR_RXCLOCK_MASK		0xf0
-#define	DART_CSR_RXCLOCK_SHIFT		4
-#define	DART_CSR_TXCLOCK_MASK		0x0f
-#define	DART_CSR_TXCLOCK_SHIFT		0
-
-#define	DART_CSR_50		0x00	/* set 1 */
-#define	DART_CSR_75		0x00	/* set 2 */
-#define	DART_CSR_110		0x01
-#define	DART_CSR_134		0x02
-#define	DART_CSR_150		0x03	/* set 2 */
-#define	DART_CSR_200		0x03	/* set 1 */
-#define	DART_CSR_300		0x04
-#define	DART_CSR_600		0x05
-#define	DART_CSR_1050		0x07	/* set 1 */
-#define	DART_CSR_1200		0x06
-#define	DART_CSR_1800		0x0a	/* set 2 */
-#define	DART_CSR_2000		0x07	/* set 2 */
-#define	DART_CSR_2400		0x08
-#define	DART_CSR_4800		0x09
-#define	DART_CSR_7200		0x0a	/* set 1 */
-#define	DART_CSR_9600		0x0b
-#define	DART_CSR_19200		0x0c	/* set 2 */
-#define	DART_CSR_38400		0x0c	/* set 1 */
-#define	DART_CSR_TIMER		0x0d
-#define	DART_CSR_IP_16X		0x0e
-#define	DART_CSR_IP_1X		0x0f
-
-/* Input Port numbers for DART_CSR_IP_ settings */
-#define	DART_IP_TXA	3
-#define	DART_IP_RXA	4
-#define	DART_IP_TXB	5
-#define	DART_IP_RXB	2
-
-/*
- * Command Register
- */
-
-#define	DART_CR_STOP_BREAK		0x70
-#define	DART_CR_START_BREAK		0x60
-#define	DART_CR_RESET_BREAK		0x50
-#define	DART_CR_RESET_ERROR		0x40
-#define	DART_CR_RESET_TX		0x30
-#define	DART_CR_RESET_RX		0x20
-#define	DART_CR_RESET_MR1		0x10
-
-#define	DART_CR_TX_DISABLE		0x08
-#define	DART_CR_TX_ENABLE		0x04
-
-#define	DART_CR_RX_DISABLE		0x02
-#define	DART_CR_RX_ENABLE		0x01
-
-/*
- * Status Register
- */
-
-#define	DART_SR_BREAK			0x80	/* break received */
-#define	DART_SR_FRAME			0x40	/* frame error */
-#define	DART_SR_PARITY			0x20	/* parity error */
-#define	DART_SR_OVERRUN			0x10
-#define	DART_SR_TX_EMPTY		0x08
-#define	DART_SR_TX_READY		0x04
-#define	DART_SR_RX_FULL			0x02	/* RX FIFO full */
-#define	DART_SR_RX_READY		0x01
-
-/*
- * Output Port Configuration Register
- */
-
-#define	DART_OPCR_TX_READY_B		0x80
-#define	DART_OPCR_OP7			0x00
-#define	DART_OPCR_TX_READY_A		0x40
-#define	DART_OPCR_OP6			0x00
-#define	DART_OPCR_RX_B			0x20
-#define	DART_OPCR_OP5			0x00
-#define	DART_OPCR_RX_A			0x10
-#define	DART_OPCR_OP4			0x00
-
-#define	DART_OPCR_RXCB			0x0c
-#define	DART_OPCR_TXCB			0x08
-#define	DART_OPCR_CT_OUTPUT		0x04
-#define	DART_OPCR_OP3			0x00
-
-#define	DART_OPCR_RXCA			0x03
-#define	DART_OPCR_TXCA			0x02
-#define	DART_OPCR_TXCA_X16		0x01
-#define	DART_OPCR_OP2			0x00
-
-/*
- * Auxiliary Control Register
- */
-
-#define	DART_ACR_BRG_SET_MASK		0x80
-#define	DART_ACR_BRG_SET_2		0x80
-#define	DART_ACR_BRG_SET_1		0x00
-
-#define	DART_ACR_CT_MASK		0x70
-#define	DART_ACR_CT_TIMER_BIT		0x40
-#define	DART_ACR_CT_TIMER_CLK_16	0x70	/* clock / 16 */
-#define	DART_ACR_CT_TIMER_CLK		0x60	/* clock / 1 */
-#define	DART_ACR_CT_TIMER_IP2_16	0x50	/* IP2 / 16 */
-#define	DART_ACR_CT_TIMER_IP2		0x40	/* IP2 / 1 */
-#define	DART_ACR_CT_COUNTER_CLK_16	0x30	/* clock / 16 */
-#define	DART_ACR_CT_COUNTER_TXCB	0x20
-#define	DART_ACR_CT_COUNTER_TXCA	0x10
-#define	DART_ACR_CT_COUNTER_IP2		0x00	/* IP2 / 1 */
-
-#define	DART_ACR_ISR_IP3_CHANGE_ENABLE	0x08
-#define	DART_ACR_ISR_IP2_CHANGE_ENABLE	0x04
-#define	DART_ACR_ISR_IP1_CHANGE_ENABLE	0x02
-#define	DART_ACR_ISR_IP0_CHANGE_ENABLE	0x01
-
-/*
- * Input Port Change Register
- */
-
-#define	DART_IPCR_IP3_CHANGED		0x80
-#define	DART_IPCR_IP2_CHANGED		0x40
-#define	DART_IPCR_IP1_CHANGED		0x20
-#define	DART_IPCR_IP0_CHANGED		0x10
-#define	DART_IPCR_IP3_LEVEL		0x08
-#define	DART_IPCR_IP2_LEVEL		0x04
-#define	DART_IPCR_IP1_LEVEL		0x02
-#define	DART_IPCR_IP0_LEVEL		0x01
-
-/*
- * Interrupt Status Register / Interrupt Mask Register
- */
-
-#define	DART_ISR_IP_CHANGE		0x80
-#define	DART_ISR_DELTA_BREAK_B		0x40
-#define	DART_ISR_RXB			0x20
-#define	DART_ISR_TXB			0x10
-#define	DART_ISR_CT			0x08
-#define	DART_ISR_DELTA_BREAK_A		0x04
-#define	DART_ISR_RXA			0x02
-#define	DART_ISR_TXA			0x01
-
-/*
- * Input Port
- */
-
-#define	DART_IP_IACK			0x40	/* read only */
-#define	DART_IP_IP5			0x20
-#define	DART_IP_IP4			0x10	/* external BRG clock */
-#define	DART_IP_IP3			0x08
-#define	DART_IP_IP2			0x04
-#define	DART_IP_IP1			0x02
-#define	DART_IP_IP0			0x01
-
-/*
- * Output Port
- */
-
-#define	DART_OP_OP7			0x80
-#define	DART_OP_OP6			0x40
-#define	DART_OP_OP5			0x20
-#define	DART_OP_OP4			0x10
-#define	DART_OP_OP3			0x08
-#define	DART_OP_OP2			0x04
-#define	DART_OP_OP1			0x02
-#define	DART_OP_OP0			0x01
diff --git a/sys/dev/ic/mc68681var.h b/sys/dev/ic/mc68681var.h
deleted file mode 100644
index fa259a00e8a..00000000000
--- a/sys/dev/ic/mc68681var.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*	$OpenBSD: mc68681var.h,v 1.2 2013/09/21 20:05:01 miod Exp $	*/
-
-/*
- * Copyright (c) 2013 Miodrag Vallat.
- *
- * Permission to use, copy, modify, and distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#define	N68681PORTS		2
-
-#define	A_PORT			0
-#define	B_PORT			1
-
-/* speed lookup table entry */
-struct mc68681_s {
-	int			 speed;
-	uint8_t			 brg_sets; /* bitmask of compatible sets */
-	uint8_t			 csr;
-};
-
-/* per-line state */
-struct mc68681_line {
-	struct tty		*tty;
-	const struct mc68681_s	*speed;
-	uint			 swflags;
-};
-
-/* per-line hardware configuration */
-struct mc68681_hw {
-	uint8_t			 dtr_op;
-	uint8_t			 rts_op;
-	uint8_t			 dcd_ip;
-	uint8_t			 dcd_active_low;
-};
-
-/* write-only chip registers values */
-struct mc68681_sw_reg {
-	uint8_t			 mr1[N68681PORTS];
-	uint8_t			 mr2[N68681PORTS];
-	uint8_t			 cr[N68681PORTS];
-	uint8_t			 acr;
-	uint8_t			 imr;
-	uint8_t			 oprs;
-	uint8_t			 opcr;
-	int			*ct;	/* timer limit in timer mode */
-};
-
-struct mc68681_softc {
-	struct device		 sc_dev;
-
-	struct mc68681_sw_reg	*sc_sw_reg;
-	struct mc68681_hw	 sc_hw[N68681PORTS];
-	struct mc68681_line	 sc_line[N68681PORTS];
-
-	int			 sc_consport;
-
-	uint8_t			(*sc_read)(void *, uint);
-	void			(*sc_write)(void *, uint, uint8_t);
-
-	struct mc68681_sw_reg	 sc_sw_reg_store;
-};
-
-void	mc68681_common_attach(struct mc68681_softc *);
-void	mc68681_intr(struct mc68681_softc *, uint8_t);