diff options
| author |   jsg <jsg@openbsd.org> | 2020-01-10 02:03:08 +0000 |
|---|---|---|
| committer | jsg <jsg@openbsd.org> | 2020-01-10 02:03:08 +0000 |
| commit | 5c65cd1a8bff70c73a1ba875e92f5e77f86bad46 (patch) | |
| tree | 094531d114da6986480c7baba0f5220e866bb27e /sys | |
| parent | remove dpt(4) driver for DPT EATA SCSI RAID (diff) | |
| download | wireguard-openbsd-5c65cd1a8bff70c73a1ba875e92f5e77f86bad46.tar.xz wireguard-openbsd-5c65cd1a8bff70c73a1ba875e92f5e77f86bad46.zip | |
drm/amdgpu: add check before enabling/disabling broadcast mode
From Guchun Chen
3517664ad07ce796d786082b1f890fcad5e7af47 in linux 4.19.y/4.19.94
6e807535dae5dbbd53bcc5e81047a20bf5eb08ea in mainline linux
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/dev/pci/drm/amd/amdgpu/df_v3_6.c | 38 |
1 files changed, 22 insertions, 16 deletions
diff --git a/sys/dev/pci/drm/amd/amdgpu/df_v3_6.c b/sys/dev/pci/drm/amd/amdgpu/df_v3_6.c index d5ebe566809..a1c941229f4 100644 --- a/sys/dev/pci/drm/amd/amdgpu/df_v3_6.c +++ b/sys/dev/pci/drm/amd/amdgpu/df_v3_6.c @@ -75,23 +75,29 @@ static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev, { u32 tmp; - /* Put DF on broadcast mode */ - adev->df_funcs->enable_broadcast_mode(adev, true); - - if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) { - tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); - tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; - tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY; - WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp); - } else { - tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); - tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; - tmp |= DF_V3_6_MGCG_DISABLE; - WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp); + if (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG) { + /* Put DF on broadcast mode */ + adev->df_funcs->enable_broadcast_mode(adev, true); + + if (enable) { + tmp = RREG32_SOC15(DF, 0, + mmDF_PIE_AON0_DfGlobalClkGater); + tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; + tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY; + WREG32_SOC15(DF, 0, + mmDF_PIE_AON0_DfGlobalClkGater, tmp); + } else { + tmp = RREG32_SOC15(DF, 0, + mmDF_PIE_AON0_DfGlobalClkGater); + tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; + tmp |= DF_V3_6_MGCG_DISABLE; + WREG32_SOC15(DF, 0, + mmDF_PIE_AON0_DfGlobalClkGater, tmp); + } + + /* Exit broadcast mode */ + adev->df_funcs->enable_broadcast_mode(adev, false); } - - /* Exit broadcast mode */ - adev->df_funcs->enable_broadcast_mode(adev, false); } static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev, |