diff options
| author |   jsg <jsg@openbsd.org> | 2018-07-03 08:42:32 +0000 |
|---|---|---|
| committer | jsg <jsg@openbsd.org> | 2018-07-03 08:42:32 +0000 |
| commit | 6d88ecd32e0d17e9b65c54cdddc45d8725bc23fe (patch) | |
| tree | f896075cf3fefd96ef1ac654e0b20c145e51e958 /sys | |
| parent | regen (diff) | |
| download | wireguard-openbsd-6d88ecd32e0d17e9b65c54cdddc45d8725bc23fe.tar.xz wireguard-openbsd-6d88ecd32e0d17e9b65c54cdddc45d8725bc23fe.zip | |
add amd speculation control cpuid bits
documented in 'AMD64 Technology Indirect Branch Control Extension'
and 'Speculative Store Bypass Disable'
ok mlarkin@ deraadt@
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/amd64/amd64/identcpu.c | 7 | ||||
| -rw-r--r-- | sys/arch/amd64/include/specialreg.h | 10 |
2 files changed, 15 insertions, 2 deletions
diff --git a/sys/arch/amd64/amd64/identcpu.c b/sys/arch/amd64/amd64/identcpu.c index 86c11b579e3..8595a0df244 100644 --- a/sys/arch/amd64/amd64/identcpu.c +++ b/sys/arch/amd64/amd64/identcpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: identcpu.c,v 1.99 2018/06/28 21:31:36 sthen Exp $ */ +/* $OpenBSD: identcpu.c,v 1.100 2018/07/03 08:42:32 jsg Exp $ */ /* $NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $ */ /* @@ -218,6 +218,11 @@ const struct { { CPUIDEDX_ITSC, "ITSC" }, }, cpu_amdspec_ebxfeatures[] = { { CPUIDEBX_IBPB, "IBPB" }, + { CPUIDEBX_IBRS, "IBRS" }, + { CPUIDEBX_STIBP, "STIBP" }, + { CPUIDEBX_SSBD, "SSBD" }, + { CPUIDEBX_VIRT_SSBD, "VIRTSSBD" }, + { CPUIDEBX_SSBD_NOTREQ, "SSBDNR" }, }, cpu_xsave_extfeatures[] = { { XSAVE_XSAVEOPT, "XSAVEOPT" }, { XSAVE_XSAVEC, "XSAVEC" }, diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h index 04c517c79a4..06921429587 100644 --- a/sys/arch/amd64/include/specialreg.h +++ b/sys/arch/amd64/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.74 2018/06/07 04:07:28 guenther Exp $ */ +/* $OpenBSD: specialreg.h,v 1.75 2018/07/03 08:42:32 jsg Exp $ */ /* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */ /* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */ @@ -302,6 +302,14 @@ * AMD CPUID function 0x80000008 EBX bits */ #define CPUIDEBX_IBPB (1ULL << 12) /* Speculation Control IBPB */ +#define CPUIDEBX_IBRS (1ULL << 14) /* Speculation Control IBRS */ +#define CPUIDEBX_STIBP (1ULL << 15) /* Speculation Control STIBP */ +#define CPUIDEBX_IBRS_ALWAYSON (1ULL << 16) /* IBRS always on mode */ +#define CPUIDEBX_STIBP_ALWAYSON (1ULL << 17) /* STIBP always on mode */ +#define CPUIDEBX_IBRS_PREF (1ULL << 18) /* IBRS preferred */ +#define CPUIDEBX_SSBD (1ULL << 24) /* Speculation Control SSBD */ +#define CPUIDEBX_VIRT_SSBD (1ULL << 25) /* Virt Spec Control SSBD */ +#define CPUIDEBX_SSBD_NOTREQ (1ULL << 26) /* SSBD not required */ #define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 15) #define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 15) |