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authorkettenis <kettenis@openbsd.org>2018-04-02 16:45:56 +0000
committerkettenis <kettenis@openbsd.org>2018-04-02 16:45:56 +0000
commitb1087d53d6870e1efa644332cadb8a7c39cb8512 (patch)
tree105fd1f4c419be1eceebc42b68501003f5c03a87 /sys
parentHave fec(4) make use of the clock framework by implementing the enet (diff)
downloadwireguard-openbsd-b1087d53d6870e1efa644332cadb8a7c39cb8512.tar.xz
wireguard-openbsd-b1087d53d6870e1efa644332cadb8a7c39cb8512.zip
Add dwpcie(4), a (minimal) driver for the Synopsys Designware PCIe core in
Root Complex mode. In its current state it probably only works on the Marvell Armada 7K and 8K SoCs, but the same core is used on many other cores as well.
Diffstat (limited to 'sys')
-rw-r--r--sys/dev/fdt/files.fdt6
1 files changed, 5 insertions, 1 deletions
diff --git a/sys/dev/fdt/files.fdt b/sys/dev/fdt/files.fdt
index b0bffd965bd..f30501a7c36 100644
--- a/sys/dev/fdt/files.fdt
+++ b/sys/dev/fdt/files.fdt
@@ -1,4 +1,4 @@
-# $OpenBSD: files.fdt,v 1.52 2018/03/31 16:35:15 kettenis Exp $
+# $OpenBSD: files.fdt,v 1.53 2018/04/02 16:45:56 kettenis Exp $
#
# Config file and device description for machine-independent FDT code.
# Included by ports that need it.
@@ -146,6 +146,10 @@ device dwdog
attach dwdog at fdt
file dev/fdt/dwdog.c dwdog
+device dwpcie: pcibus
+attach dwpcie at fdt
+file dev/fdt/dwpcie.c dwpcie
+
device mvclock
attach mvclock at fdt
file dev/fdt/mvclock.c mvclock