Fix sorting and ordering.

ok bmercer@

1 files changed, 82 insertions, 59 deletions

diff --git a/sys/arch/armv7/omap/omap3_prcmreg.h b/sys/arch/armv7/omap/omap3_prcmreg.h
index 3d41d170655..f9f3f71cf2b 100644
--- a/sys/arch/armv7/omap/omap3_prcmreg.h
+++ b/sys/arch/armv7/omap/omap3_prcmreg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: omap3_prcmreg.h,v 1.1 2013/09/04 14:38:30 patrick Exp $ */
+/* $OpenBSD: omap3_prcmreg.h,v 1.2 2013/10/23 11:11:31 rapha Exp $ */
 /*
  * Copyright (c) 2007, 2009, 2012 Dale Rahn <drahn@dalerahn.com>
  *
@@ -25,7 +25,6 @@
 #define	CM_CLKSEL2_PLL_IVA2	0x0044
 #define	CM_CLKSTCTRL_IVA2	0x0048
 #define	CM_CLKSTST_IVA2		0x004c
-
 #define	CM_CLKSEL_MPU		0x0940
 #define	CM_CLKSTCTRL_MPU	0x0948
 #define	RM_RSTST_MPU		0x0958
@@ -35,23 +34,28 @@
 #define	PM_EVEGENOFFTIM_MPU	0x09DC
 #define	PM_PWSTCTRL_MPU		0x09E0
 #define	PM_PWSTST_MPU		0x09E4
-
-#define	CM_ICLKEN1_CORE	0x0a10
+#define	CM_FCLKEN1_CORE		0x0a00
+#define	CM_FCLKEN1_CORE_MSK	0x41fffe00
+#define	CM_FCLKEN2_CORE		0x0a04
+#define	CM_FCLKEN2_CORE_MSK	0x00000000
+#define	CM_FCLKEN3_CORE		0x0a08
+#define	CM_FCLKEN3_CORE_MSK	0x00000007
+#define	CM_ICLKEN1_CORE		0x0a10
 #define	CM_ICLKEN1_CORE_MSK	0x7ffffed2
-#define	CM_ICLKEN2_CORE	0x0a14
+#define	CM_ICLKEN2_CORE		0x0a14
 #define	CM_ICLKEN2_CORE_MSK	0x0000001f
-#define	CM_ICLKEN3_CORE	0x0a18
+#define	CM_ICLKEN3_CORE		0x0a18
 #define	CM_ICLKEN3_CORE_MSK	0x00000004
-#define	CM_ICLKEN4_CORE	0x0a1C
-#define	CM_IDLEST1_CORE	0x0a20
-#define	CM_IDLEST2_CORE	0x0a24
-#define	CM_IDLEST4_CORE	0x0a2C
+#define	CM_ICLKEN4_CORE		0x0a1C
+#define	CM_IDLEST1_CORE		0x0a20
+#define	CM_IDLEST2_CORE		0x0a24
+#define	CM_IDLEST4_CORE		0x0a2C
 #define	CM_AUTOIDLE1_CORE	0x0a30
 #define	CM_AUTOIDLE2_CORE	0x0a34
 #define	CM_AUTOIDLE3_CORE	0x0a38
 #define	CM_AUTOIDLE4_CORE	0x0a3C
-#define	CM_CLKSEL1_CORE	0x0a40
-#define	CM_CLKSEL2_CORE	0x0a44
+#define	CM_CLKSEL1_CORE		0x0a40
+#define	CM_CLKSEL2_CORE		0x0a44
 #define	CM_CLKSTCTRL_CORE	0x0a48
 #define	PM_WKEN1_CORE		0x0aA0
 #define	PM_WKEN2_CORE		0x0aA4
@@ -62,7 +66,6 @@
 #define	PM_PWSTST_CORE		0x0aE4
 #define	CM_FCLKEN_GFX		0x0b00
 #define	CM_ICLKEN_GFX		0x0b10
-
 #define	CM_IDLEST_GFX		0x0b20
 #define	CM_CLKSEL_GFX		0x0b40
 #define	CM_CLKSTCTRL_GFX	0x0b48
@@ -72,16 +75,9 @@
 #define	PM_PWSTCTRL_GFX		0x0bE0
 #define	PM_PWSTST_GFX		0x0bE4
 #define	CM_FCLKEN_WKUP		0x0c00
-#define		CM_FCLKEN_WKUP_GPT1	1
-#define		CM_FCLKEN_WKUP_GPIOS	4
-#define		CM_FCLKEN_WKUP_MPU_WDT	8
-#define	CM_ICLKEN_WKUP		0xc10
-#define		CM_ICLKEN_WKUP_GPT1	0x01
-#define		CM_ICLKEN_WKUP_32KSYNC	0x02
-#define		CM_ICLKEN_WKUP_GPIOS	0x04
-#define		CM_ICLKEN_WKUP_MPU_WDT	0x08
-#define		CM_ICLKEN_WKUP_WDT1	0x10
-#define		CM_ICLKEN_WKUP_OMAPCTRL	0x20
+#define CM_FCLKEN_WKUP_MSK	0x00000029
+#define	CM_ICLKEN_WKUP		0x0c10
+#define CM_ICLKEN_WKUP_MSK	0x0000002d
 #define	CM_IDLEST_WKUP		0x0c20
 #define	CM_AUTOIDLE_WKUP	0x0c30
 #define	CM_CLKSEL_WKUP		0x0c40
@@ -108,33 +104,24 @@
 #define	CM_SLEEPDEP_PER		0x1044
 #define	CM_CLKSTCTRL_PER	0x1048
 #define	CM_CLKSTST_PER		0x104C
+#define	CM_CLKSEL1_EMU		0x1140
+#define	CM_CLKSTCTRL_EMU	0x1148
+#define	CM_CLKSTST_EMU		0x114C
+#define	CM_CLKSEL2_EMU		0x1150
+#define	CM_CLKSEL3_EMU		0x1154
+#define	CM_POLCTRL		0x129C
+#define	CM_IDLEST_NEON		0x1320
+#define	CM_CLKSTCTRL_NEON	0x1348
+#define	CM_FCLKEN_USBHOST	0x1400
+#define	CM_FCLKEN_USBHOST_MSK	0x00000003
+#define	CM_ICLKEN_USBHOST	0x1410
+#define	CM_ICLKEN_USBHOST_MSK	0x00000001
+#define	CM_IDLEST_USBHOST	0x1420
+#define	CM_AUTOIDLE_USBHOST	0x1430
+#define	CM_SLEEPDEP_USBHOST	0x1444
+#define	CM_CLKSTCTRL_USBHOST	0x1448
+#define	CM_CLKSTST_USBHOST	0x144C
 
-#define	CM_CLKSEL1_EMU		0x5140
-#define	CM_CLKSTCTRL_EMU	0x5148
-#define	CM_CLKSTST_EMU		0x514C
-#define	CM_CLKSEL2_EMU		0x5150
-#define	CM_CLKSEL3_EMU		0x5154
-
-#define	CM_POLCTRL		0x529C
-
-#define	CM_IDLEST_NEON		0x5320
-#define	CM_CLKSTCTRL_NEON	0x5348
-
-#define	CM_FCLKEN_USBHOST	0x5400
-#define	CM_ICLKEN_USBHOST	0x5410
-#define	CM_IDLEST_USBHOST	0x5420
-#define	CM_AUTOIDLE_USBHOST	0x5430
-#define	CM_SLEEPDEP_USBHOST	0x5444
-#define	CM_CLKSTCTRL_USBHOST	0x5448
-#define	CM_CLKSTST_USBHOST	0x544C
-
-/* from prcmvar.h */
-#define	CM_FCLKEN1_CORE		0x0a00
-#define	CM_FCLKEN1_CORE_MSK	0x41fffe00
-#define	CM_FCLKEN2_CORE		0x0a04
-#define	CM_FCLKEN2_CORE_MSK	0x00000000
-#define	CM_FCLKEN3_CORE		0x0a08
-#define	CM_FCLKEN3_CORE_MSK	0x00000007
 
 #define	PRCM_REG_CORE_CLK1	0
 #define	PRCM_REG_CORE_CLK1_FADDR	CM_FCLKEN1_CORE
@@ -182,16 +169,52 @@
 #define	PRCM_REG_CORE_CLK3_FMASK	CM_FCLKEN3_CORE_MSK
 #define	PRCM_REG_CORE_CLK3_IMASK	CM_ICLKEN3_CORE_MSK
 #define	PRCM_REG_CORE_CLK3_BASE	(PRCM_REG_CORE_CLK3*32)
+#define		PRCM_CORE_EN_USBTLL	(PRCM_REG_CORE_CLK3_BASE + 2)
+#define		PRCM_CORE_EN_TS		(PRCM_REG_CORE_CLK3_BASE + 1)
+#define		PRCM_CORE_EN_CPEFUSE	(PRCM_REG_CORE_CLK3_BASE + 0)
 
-#define	CM_CORE_EN_USBTLL	(PRCM_REG_CORE_CLK3_BASE + 2)
-#define	CM_CORE_EN_TS		(PRCM_REG_CORE_CLK3_BASE + 1)
-#define	CM_CORE_EN_CPEFUSE	(PRCM_REG_CORE_CLK3_BASE + 0)
+#define PRCM_REG_WKUP		3
+#define PRCM_REG_WKUP_FADDR		CM_FCLKEN_WKUP
+#define PRCM_REG_WKUP_IADDR		CM_ICLKEN_WKUP
+#define PRCM_REG_WKUP_FMASK		CM_FCLKEN_WKUP_MSK
+#define PRCM_REG_WKUP_IMASK		CM_ICLKEN_WKUP_MSK
+#define PRCM_REG_WKUP_BASE (PRCM_REG_WKUP*32)
+#define		PRCM_CLK_EN_MPU_WDT	(PRCM_REG_WKUP_BASE + 5)
+#define		PRCM_CLK_EN_GPIO1	(PRCM_REG_WKUP_BASE + 3)
+#define		PRCM_CLK_EN_32KSYNC	(PRCM_REG_WKUP_BASE + 2)
+#define		PRCM_CLK_EN_GPT1	(PRCM_REG_WKUP_BASE + 0)
 
-#define	PRCM_REG_USBHOST	3
-#define	PRCM_REG_USBHOST_FADDR	0x1400
-#define	PRCM_REG_USBHOST_IADDR	0x1410
-#define	PRCM_REG_USBHOST_FMASK	0x3
-#define	PRCM_REG_USBHOST_IMASK	0x1
-#define	PRCM_REG_USBHOST_BASE	(PRCM_REG_USBHOST*32)
+#define PRCM_REG_PER		4
+#define PRCM_REG_PER_FADDR		CM_FCLKEN_PER
+#define PRCM_REG_PER_IADDR		CM_ICLKEN_PER
+#define PRCM_REG_PER_FMASK		CM_FCLKEN_PER_MSK
+#define PRCM_REG_PER_IMASK		CM_ICLKEN_PER_MSK
+#define PRCM_REG_PER_BASE (PRCM_REG_PER*32)
+#define		PRCM_CLK_EN_GPIO6	(PRCM_REG_PER_BASE + 17)
+#define		PRCM_CLK_EN_GPIO5	(PRCM_REG_PER_BASE + 16)
+#define		PRCM_CLK_EN_GPIO4	(PRCM_REG_PER_BASE + 15)
+#define		PRCM_CLK_EN_GPIO3	(PRCM_REG_PER_BASE + 14)
+#define		PRCM_CLK_EN_GPIO2	(PRCM_REG_PER_BASE + 13)
+#define		PRCM_CLK_EN_WDT3	(PRCM_REG_PER_BASE + 12)
+#define		PRCM_CLK_EN_UART3	(PRCM_REG_PER_BASE + 11)
+#define		PRCM_CLK_EN_GPT9	(PRCM_REG_PER_BASE + 10)
+#define		PRCM_CLK_EN_GPT8	(PRCM_REG_PER_BASE + 9)
+#define		PRCM_CLK_EN_GPT7	(PRCM_REG_PER_BASE + 8)
+#define		PRCM_CLK_EN_GPT6	(PRCM_REG_PER_BASE + 7)
+#define		PRCM_CLK_EN_GPT5	(PRCM_REG_PER_BASE + 6)
+#define		PRCM_CLK_EN_GPT4	(PRCM_REG_PER_BASE + 5)
+#define		PRCM_CLK_EN_GPT3	(PRCM_REG_PER_BASE + 4)
+#define		PRCM_CLK_EN_GPT2	(PRCM_REG_PER_BASE + 3)
+#define		PRCM_CLK_EN_MCBSP4	(PRCM_REG_PER_BASE + 2)
+#define		PRCM_CLK_EN_MCBSP3	(PRCM_REG_PER_BASE + 1)
+#define		PRCM_CLK_EN_MCBSP2	(PRCM_REG_PER_BASE + 0)
 
-#define	PRCM_CLK_EN_USB		(PRCM_REG_USBHOST_BASE + 0)
+#define	PRCM_REG_USBHOST	5
+#define	PRCM_REG_USBHOST_FADDR	CM_FCLKEN_USBHOST
+#define	PRCM_REG_USBHOST_IADDR	CM_ICLKEN_USBHOST
+#define	PRCM_REG_USBHOST_FMASK	CM_FCLKEN_USBHOST_MSK
+#define	PRCM_REG_USBHOST_IMASK	CM_ICLKEN_USBHOST_MSK
+#define	PRCM_REG_USBHOST_BASE	(PRCM_REG_USBHOST*32)
+#define		PRCM_CLK_EN_USBHOST2	(PRCM_REG_USBHOST_BASE + 1)
+#define		PRCM_CLK_EN_USBHOST1	(PRCM_REG_USBHOST_BASE + 0)
+#define		PRCM_CLK_EN_USB		(PRCM_REG_USBHOST_BASE + 0)