diff options
| -rw-r--r-- | sys/arch/arm/arm/cpu.c | 4 | ||||
| -rw-r--r-- | sys/arch/arm/arm/cpufunc.c | 3 | ||||
| -rw-r--r-- | sys/arch/arm/include/armreg.h | 4 |
3 files changed, 8 insertions, 3 deletions
diff --git a/sys/arch/arm/arm/cpu.c b/sys/arch/arm/arm/cpu.c index 3be661d796b..5c184417342 100644 --- a/sys/arch/arm/arm/cpu.c +++ b/sys/arch/arm/arm/cpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.c,v 1.36 2017/01/05 16:16:17 patrick Exp $ */ +/* $OpenBSD: cpu.c,v 1.37 2017/04/24 18:15:16 kettenis Exp $ */ /* $NetBSD: cpu.c,v 1.56 2004/04/14 04:01:49 bsh Exp $ */ @@ -126,6 +126,8 @@ const struct cpuidtab cpuids[] = { generic_steppings }, { CPU_ID_CORTEX_A9_R4, CPU_CLASS_ARMv7, "ARM Cortex A9 R4", generic_steppings }, + { CPU_ID_CORTEX_A12, CPU_CLASS_ARMv7, "ARM Cortex A12", + generic_steppings }, { CPU_ID_CORTEX_A15, CPU_CLASS_ARMv7, "ARM Cortex A15", generic_steppings }, { CPU_ID_CORTEX_A15_R1, CPU_CLASS_ARMv7, "ARM Cortex A15 R1", diff --git a/sys/arch/arm/arm/cpufunc.c b/sys/arch/arm/arm/cpufunc.c index b1de93b1c6b..c91108e7066 100644 --- a/sys/arch/arm/arm/cpufunc.c +++ b/sys/arch/arm/arm/cpufunc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cpufunc.c,v 1.50 2017/01/06 00:06:02 jsg Exp $ */ +/* $OpenBSD: cpufunc.c,v 1.51 2017/04/24 18:15:16 kettenis Exp $ */ /* $NetBSD: cpufunc.c,v 1.65 2003/11/05 12:53:15 scw Exp $ */ /* @@ -377,6 +377,7 @@ armv7_setup() #endif /* FALLTHROUGH */ case CPU_ID_CORTEX_A7: + case CPU_ID_CORTEX_A12: case CPU_ID_CORTEX_A15: case CPU_ID_CORTEX_A17: /* Set SMP to allow LDREX/STREX */ diff --git a/sys/arch/arm/include/armreg.h b/sys/arch/arm/include/armreg.h index 6c88e85b47c..877eaf369c4 100644 --- a/sys/arch/arm/include/armreg.h +++ b/sys/arch/arm/include/armreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: armreg.h,v 1.39 2017/01/04 00:40:49 jsg Exp $ */ +/* $OpenBSD: armreg.h,v 1.40 2017/04/24 18:15:16 kettenis Exp $ */ /* $NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $ */ /* @@ -139,6 +139,8 @@ #define CPU_ID_CORTEX_A9_R3 0x413fc090 #define CPU_ID_CORTEX_A9_R4 0x414fc090 #define CPU_ID_CORTEX_A9_MASK 0xff0ffff0 +#define CPU_ID_CORTEX_A12 0x410fc0d0 +#define CPU_ID_CORTEX_A12_MASK 0xff0ffff0 #define CPU_ID_CORTEX_A15 0x410fc0f0 #define CPU_ID_CORTEX_A15_R1 0x411fc0f0 #define CPU_ID_CORTEX_A15_R2 0x412fc0f0 |