diff options
| -rw-r--r-- | sys/arch/arm/arm/cpu.c | 16 | ||||
| -rw-r--r-- | sys/arch/arm/arm/cpufunc.c | 111 | ||||
| -rw-r--r-- | sys/arch/arm/arm/cpufunc_asm_arm9.S | 254 | ||||
| -rw-r--r-- | sys/arch/arm/arm/pmap.c | 23 | ||||
| -rw-r--r-- | sys/arch/arm/conf/files.arm | 6 | ||||
| -rw-r--r-- | sys/arch/arm/include/armreg.h | 6 | ||||
| -rw-r--r-- | sys/arch/arm/include/cpuconf.h | 9 | ||||
| -rw-r--r-- | sys/arch/arm/include/cpufunc.h | 30 | ||||
| -rw-r--r-- | sys/arch/arm/include/pmap.h | 5 |
9 files changed, 14 insertions, 446 deletions
diff --git a/sys/arch/arm/arm/cpu.c b/sys/arch/arm/arm/cpu.c index 3649ee51145..c5cae81edd7 100644 --- a/sys/arch/arm/arm/cpu.c +++ b/sys/arch/arm/arm/cpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.c,v 1.23 2016/03/18 06:54:21 jsg Exp $ */ +/* $OpenBSD: cpu.c,v 1.24 2016/03/18 13:16:02 jsg Exp $ */ /* $NetBSD: cpu.c,v 1.56 2004/04/14 04:01:49 bsh Exp $ */ @@ -84,7 +84,6 @@ cpu_attach(struct device *dv) enum cpu_class { CPU_CLASS_NONE, - CPU_CLASS_ARM9TDMI, CPU_CLASS_ARM9ES, CPU_CLASS_ARM9EJS, CPU_CLASS_ARM10E, @@ -193,22 +192,14 @@ struct cpuidtab { }; const struct cpuidtab cpuids[] = { - { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", - generic_steppings }, - { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", - generic_steppings }, { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", generic_steppings }, - { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", - generic_steppings }, { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", generic_steppings }, { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", generic_steppings }, { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", generic_steppings }, - { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", - generic_steppings }, { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", generic_steppings }, @@ -329,7 +320,6 @@ struct cpu_classtab { const struct cpu_classtab cpu_classes[] = { { "unknown", NULL }, /* CPU_CLASS_NONE */ - { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */ { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */ { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */ { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */ @@ -399,7 +389,6 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci) printf("%s:", dv->dv_xname); switch (cpu_class) { - case CPU_CLASS_ARM9TDMI: case CPU_CLASS_ARM9ES: case CPU_CLASS_ARM9EJS: case CPU_CLASS_ARM10E: @@ -454,9 +443,6 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci) skip_pcache: switch (cpu_class) { -#ifdef CPU_ARM9 - case CPU_CLASS_ARM9TDMI: -#endif #ifdef CPU_ARM9E case CPU_CLASS_ARM9ES: case CPU_CLASS_ARM9EJS: diff --git a/sys/arch/arm/arm/cpufunc.c b/sys/arch/arm/arm/cpufunc.c index 462f1bceaf9..5409ffc0fd7 100644 --- a/sys/arch/arm/arm/cpufunc.c +++ b/sys/arch/arm/arm/cpufunc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cpufunc.c,v 1.29 2016/03/18 06:54:21 jsg Exp $ */ +/* $OpenBSD: cpufunc.c,v 1.30 2016/03/18 13:16:02 jsg Exp $ */ /* $NetBSD: cpufunc.c,v 1.65 2003/11/05 12:53:15 scw Exp $ */ /* @@ -97,64 +97,6 @@ int arm_dcache_align_mask; /* 1 == use cpu_sleep(), 0 == don't */ int cpu_do_powersave; -#ifdef CPU_ARM9 -struct cpu_functions arm9_cpufuncs = { - /* CPU functions */ - - cpufunc_id, /* id */ - cpufunc_nullop, /* cpwait */ - - /* MMU functions */ - - cpufunc_control, /* control */ - cpufunc_domains, /* Domain */ - arm9_setttb, /* Setttb */ - cpufunc_dfsr, /* dfsr */ - cpufunc_dfar, /* dfar */ - cpufunc_ifsr, /* ifsr */ - cpufunc_ifar, /* ifar */ - - /* TLB functions */ - - armv4_tlb_flushID, /* tlb_flushID */ - arm9_tlb_flushID_SE, /* tlb_flushID_SE */ - armv4_tlb_flushI, /* tlb_flushI */ - (void *)armv4_tlb_flushI, /* tlb_flushI_SE */ - armv4_tlb_flushD, /* tlb_flushD */ - armv4_tlb_flushD_SE, /* tlb_flushD_SE */ - - /* Cache operations */ - - arm9_icache_sync_all, /* icache_sync_all */ - arm9_icache_sync_range, /* icache_sync_range */ - - /* ...cache in write-though mode... */ - arm9_dcache_wbinv_all, /* dcache_wbinv_all */ - arm9_dcache_wbinv_range, /* dcache_wbinv_range */ - arm9_dcache_wbinv_range, /* dcache_inv_range */ - arm9_dcache_wb_range, /* dcache_wb_range */ - - arm9_idcache_wbinv_all, /* idcache_wbinv_all */ - arm9_idcache_wbinv_range, /* idcache_wbinv_range */ - - cpufunc_nullop, /* sdcache_wbinv_all */ - (void *)cpufunc_nullop, /* sdcache_wbinv_range */ - (void *)cpufunc_nullop, /* sdcache_inv_range */ - (void *)cpufunc_nullop, /* sdcache_wb_range */ - - /* Other functions */ - - cpufunc_nullop, /* flush_prefetchbuf */ - armv4_drain_writebuf, /* drain_writebuf */ - - (void *)cpufunc_nullop, /* sleep */ - - /* Soft functions */ - arm9_context_switch, /* context_switch */ - arm9_setup /* cpu setup */ -}; -#endif /* CPU_ARM9 */ - #if defined(CPU_ARM9E) || defined(CPU_ARM10) struct cpu_functions armv5_ec_cpufuncs = { /* CPU functions */ @@ -567,8 +509,7 @@ struct cpu_functions cpufuncs; u_int cputype; u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */ -#if defined(CPU_ARM9) || \ - defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_ARM11) || \ +#if defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_ARM11) || \ defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) static void get_cachetype_cp15 (void); @@ -865,23 +806,6 @@ set_cpufuncs() * CPU type where we want to use it by default, then we set it. */ -#ifdef CPU_ARM9 - if (((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD || - (cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_TI) && - (cputype & 0x0000f000) == 0x00009000) { - cpufuncs = arm9_cpufuncs; - cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */ - get_cachetype_cp15(); - arm9_dcache_sets_inc = 1U << arm_dcache_l2_linesize; - arm9_dcache_sets_max = - (1U << (arm_dcache_l2_linesize + arm_dcache_l2_nsets)) - - arm9_dcache_sets_inc; - arm9_dcache_index_inc = 1U << (32 - arm_dcache_l2_assoc); - arm9_dcache_index_max = 0U - arm9_dcache_index_inc; - pmap_pte_init_arm9(); - return 0; - } -#endif /* CPU_ARM9 */ #if defined(CPU_ARM9E) || defined(CPU_ARM10) if (cputype == CPU_ID_ARM926EJS || cputype == CPU_ID_ARM1026EJS) { cpufuncs = armv5_ec_cpufuncs; @@ -1130,37 +1054,6 @@ set_cpufuncs() * CPU Setup code */ -#ifdef CPU_ARM9 -void -arm9_setup() -{ - int cpuctrl, cpuctrlmask; - - cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_AFLT_ENABLE; - cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE - | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE - | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE - | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE - | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_VECRELOC - | CPU_CONTROL_ROUNDROBIN; - - if (vector_page == ARM_VECTORS_HIGH) - cpuctrl |= CPU_CONTROL_VECRELOC; - - /* Clear out the cache */ - cpu_idcache_wbinv_all(); - - /* Set the control register */ - curcpu()->ci_ctrl = cpuctrl; - cpu_control(cpuctrlmask, cpuctrl); - -} -#endif /* CPU_ARM9 */ - #if defined(CPU_ARM9E) || defined(CPU_ARM10) void arm9e_setup() diff --git a/sys/arch/arm/arm/cpufunc_asm_arm9.S b/sys/arch/arm/arm/cpufunc_asm_arm9.S deleted file mode 100644 index 7864d093e20..00000000000 --- a/sys/arch/arm/arm/cpufunc_asm_arm9.S +++ /dev/null @@ -1,254 +0,0 @@ -/* $OpenBSD: cpufunc_asm_arm9.S,v 1.1 2008/09/11 02:38:14 kevlo Exp $ */ -/* $NetBSD: cpufunc_asm_arm9.S,v 1.6 2007/10/17 19:53:29 garbled Exp $ */ - -/* - * Copyright (c) 2001, 2004 ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the company may not be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * ARM9 assembly functions for CPU / MMU / TLB specific operations - */ - -#include <machine/cpu.h> -#include <machine/asm.h> - -/* - * Functions to set the MMU Translation Table Base register - * - * We need to clean and flush the cache as it uses virtual - * addresses that are about to change. - */ -ENTRY(arm9_setttb) - stmfd sp!, {r0, lr} - bl _C_LABEL(arm9_idcache_wbinv_all) - ldmfd sp!, {r0, lr} - - mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ - - mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ - mov pc, lr - -/* - * TLB functions - */ -ENTRY(arm9_tlb_flushID_SE) - mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ - mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ - mov pc, lr - -/* - * Cache operations. For the entire cache we use the set/index - * operations. - */ - s_max .req r0 - i_max .req r1 - s_inc .req r2 - i_inc .req r3 - -ENTRY_NP(arm9_icache_sync_range) - ldr ip, .Larm9_line_size - cmp r1, #0x4000 - bcs .Larm9_icache_sync_all - ldr ip, [ip] - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 -.Larm9_sync_next: - mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ - mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ - add r0, r0, ip - subs r1, r1, ip - bpl .Larm9_sync_next - mov pc, lr - -ENTRY_NP(arm9_icache_sync_all) -.Larm9_icache_sync_all: - /* - * We assume that the code here can never be out of sync with the - * dcache, so that we can safely flush the Icache and fall through - * into the Dcache cleaning code. - */ - mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ - /* Fall through to clean Dcache. */ - -.Larm9_dcache_wb: - ldr ip, .Larm9_cache_data - ldmia ip, {s_max, i_max, s_inc, i_inc} -.Lnext_set: - orr ip, s_max, i_max -.Lnext_index: - mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */ - sub ip, ip, i_inc - tst ip, i_max /* Index 0 is last one */ - bne .Lnext_index /* Next index */ - mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */ - subs s_max, s_max, s_inc - bpl .Lnext_set /* Next set */ - mov pc, lr - -.Larm9_line_size: - .word _C_LABEL(arm_pdcache_line_size) - -ENTRY(arm9_dcache_wb_range) - ldr ip, .Larm9_line_size - cmp r1, #0x4000 - bcs .Larm9_dcache_wb - ldr ip, [ip] - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 -.Larm9_wb_next: - mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ - add r0, r0, ip - subs r1, r1, ip - bpl .Larm9_wb_next - mov pc, lr - -ENTRY(arm9_dcache_wbinv_range) - ldr ip, .Larm9_line_size - cmp r1, #0x4000 - bcs .Larm9_dcache_wbinv_all - ldr ip, [ip] - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 -.Larm9_wbinv_next: - mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */ - add r0, r0, ip - subs r1, r1, ip - bpl .Larm9_wbinv_next - mov pc, lr - -/* - * Note, we must not invalidate everything. If the range is too big we - * must use wb-inv of the entire cache. - */ -ENTRY(arm9_dcache_inv_range) - ldr ip, .Larm9_line_size - cmp r1, #0x4000 - bcs .Larm9_dcache_wbinv_all - ldr ip, [ip] - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 -.Larm9_inv_next: - mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */ - add r0, r0, ip - subs r1, r1, ip - bpl .Larm9_inv_next - mov pc, lr - -ENTRY(arm9_idcache_wbinv_range) - ldr ip, .Larm9_line_size - cmp r1, #0x4000 - bcs .Larm9_idcache_wbinv_all - ldr ip, [ip] - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 -.Larm9_id_wbinv_next: - mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ - mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */ - add r0, r0, ip - subs r1, r1, ip - bpl .Larm9_id_wbinv_next - mov pc, lr - -ENTRY_NP(arm9_idcache_wbinv_all) -.Larm9_idcache_wbinv_all: - /* - * We assume that the code here can never be out of sync with the - * dcache, so that we can safely flush the Icache and fall through - * into the Dcache purging code. - */ - mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ - /* Fall through to purge Dcache. */ - -ENTRY(arm9_dcache_wbinv_all) -.Larm9_dcache_wbinv_all: - ldr ip, .Larm9_cache_data - ldmia ip, {s_max, i_max, s_inc, i_inc} -.Lnext_set_inv: - orr ip, s_max, i_max -.Lnext_index_inv: - mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */ - sub ip, ip, i_inc - tst ip, i_max /* Index 0 is last one */ - bne .Lnext_index_inv /* Next index */ - mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */ - subs s_max, s_max, s_inc - bpl .Lnext_set_inv /* Next set */ - mov pc, lr - -.Larm9_cache_data: - .word _C_LABEL(arm9_dcache_sets_max) - -/* - * Context switch. - * - * These is the CPU-specific parts of the context switcher cpu_switch() - * These functions actually perform the TTB reload. - */ -ENTRY(arm9_context_switch) - /* - * We can assume that the caches will only contain kernel addresses - * at this point. So no need to flush them again. - */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */ - mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */ - - /* Paranoia -- make sure the pipeline is empty. */ - nop - nop - nop - mov pc, lr - - .bss - -/* XXX The following macros should probably be moved to asm.h */ -#define _DATA_OBJECT(x) .globl x; .type x,_ASM_TYPE_OBJECT; x: -#define C_OBJECT(x) _DATA_OBJECT(_C_LABEL(x)) - -/* - * Parameters for the cache cleaning code. Note that the order of these - * four variables is assumed in the code above. Hence the reason for - * declaring them in the assembler file. - */ - .align 0 -C_OBJECT(arm9_dcache_sets_max) - .space 4 -C_OBJECT(arm9_dcache_index_max) - .space 4 -C_OBJECT(arm9_dcache_sets_inc) - .space 4 -C_OBJECT(arm9_dcache_index_inc) - .space 4 diff --git a/sys/arch/arm/arm/pmap.c b/sys/arch/arm/arm/pmap.c index 8fc11c8964c..62d098d88d9 100644 --- a/sys/arch/arm/arm/pmap.c +++ b/sys/arch/arm/arm/pmap.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pmap.c,v 1.59 2016/03/18 06:54:21 jsg Exp $ */ +/* $OpenBSD: pmap.c,v 1.60 2016/03/18 13:16:02 jsg Exp $ */ /* $NetBSD: pmap.c,v 1.147 2004/01/18 13:03:50 scw Exp $ */ /* @@ -4438,27 +4438,6 @@ pmap_pte_init_generic(void) pmap_copy_page_func = pmap_copy_page_generic; pmap_zero_page_func = pmap_zero_page_generic; } - -#if defined(CPU_ARM9) -void -pmap_pte_init_arm9(void) -{ - - /* - * ARM9 is compatible with generic, but we want to use - * write-through caching for now. - */ - pmap_pte_init_generic(); - - pte_l1_s_cache_mode = L1_S_C; - pte_l2_l_cache_mode = L2_C; - pte_l2_s_cache_mode = L2_C; - - pte_l1_s_cache_mode_pt = L1_S_C; - pte_l2_l_cache_mode_pt = L2_C; - pte_l2_s_cache_mode_pt = L2_C; -} -#endif /* CPU_ARM9 */ #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ #if defined(CPU_ARM10) diff --git a/sys/arch/arm/conf/files.arm b/sys/arch/arm/conf/files.arm index 9754822c249..fefb206b4ce 100644 --- a/sys/arch/arm/conf/files.arm +++ b/sys/arch/arm/conf/files.arm @@ -1,4 +1,4 @@ -# $OpenBSD: files.arm,v 1.29 2016/03/18 06:54:21 jsg Exp $ +# $OpenBSD: files.arm,v 1.30 2016/03/18 13:16:02 jsg Exp $ # $NetBSD: files.arm,v 1.76 2003/11/05 12:53:15 scw Exp $ # generic networking files @@ -39,10 +39,8 @@ file arch/arm/arm/bcopyinout.S file arch/arm/arm/copystr.S file arch/arm/arm/cpufunc.c file arch/arm/arm/cpufunc_asm.S -file arch/arm/arm/cpufunc_asm_arm9.S cpu_arm9 file arch/arm/arm/cpufunc_asm_arm10.S cpu_arm9e | cpu_arm10 -file arch/arm/arm/cpufunc_asm_armv4.S cpu_arm9 | cpu_arm9e | - cpu_arm10 | +file arch/arm/arm/cpufunc_asm_armv4.S cpu_arm9e | cpu_arm10 | cpu_sa110 | cpu_sa1100 | cpu_sa1110 | diff --git a/sys/arch/arm/include/armreg.h b/sys/arch/arm/include/armreg.h index f818c8c0fad..c5eb5e06f98 100644 --- a/sys/arch/arm/include/armreg.h +++ b/sys/arch/arm/include/armreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: armreg.h,v 1.20 2016/03/18 06:54:21 jsg Exp $ */ +/* $OpenBSD: armreg.h,v 1.21 2016/03/18 13:16:02 jsg Exp $ */ /* $NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $ */ /* @@ -176,10 +176,7 @@ #define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ /* Post-ARM7 CPUs */ -#define CPU_ID_ARM920T 0x41129200 -#define CPU_ID_ARM922T 0x41029220 #define CPU_ID_ARM926EJS 0x41069260 -#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ @@ -190,7 +187,6 @@ #define CPU_ID_ARM1136JSR1 0x4117b360 #define CPU_ID_SA110 0x4401a100 #define CPU_ID_SA1100 0x4401a110 -#define CPU_ID_TI925T 0x54029250 #define CPU_ID_SA1110 0x6901b110 #define CPU_ID_IXP1200 0x6901c120 #define CPU_ID_80200 0x69052000 diff --git a/sys/arch/arm/include/cpuconf.h b/sys/arch/arm/include/cpuconf.h index e188ef12005..0993a415169 100644 --- a/sys/arch/arm/include/cpuconf.h +++ b/sys/arch/arm/include/cpuconf.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpuconf.h,v 1.8 2016/03/18 06:54:21 jsg Exp $ */ +/* $OpenBSD: cpuconf.h,v 1.9 2016/03/18 13:16:02 jsg Exp $ */ /* $NetBSD: cpuconf.h,v 1.7 2003/05/23 00:57:24 ichiro Exp $ */ /* @@ -48,8 +48,7 @@ /* * Determine which ARM architecture versions are configured. */ -#if (defined(CPU_ARM9) || \ - defined(CPU_SA1100) || defined(CPU_SA1110) || \ +#if (defined(CPU_SA1100) || defined(CPU_SA1110) || \ defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425)) #define ARM_ARCH_4 1 #else @@ -91,8 +90,8 @@ * protection is not used, TEX/AP is used instead. */ -#if (defined(CPU_ARM9) || defined(CPU_ARM9E) || \ - defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_ARMv7) ) +#if (defined(CPU_ARM9E) || defined(CPU_ARM10) || \ + defined(CPU_ARM11) || defined(CPU_ARMv7) ) #define ARM_MMU_GENERIC 1 #else #define ARM_MMU_GENERIC 0 diff --git a/sys/arch/arm/include/cpufunc.h b/sys/arch/arm/include/cpufunc.h index 1c096a19e58..0f3d65b16e5 100644 --- a/sys/arch/arm/include/cpufunc.h +++ b/sys/arch/arm/include/cpufunc.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpufunc.h,v 1.17 2016/03/18 06:54:21 jsg Exp $ */ +/* $OpenBSD: cpufunc.h,v 1.18 2016/03/18 13:16:02 jsg Exp $ */ /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ /* @@ -250,32 +250,6 @@ void sa1_cache_syncI_rng (vaddr_t start, vsize_t end); #endif -#ifdef CPU_ARM9 -void arm9_setttb (u_int); - -void arm9_tlb_flushID_SE (u_int); - -void arm9_icache_sync_all (void); -void arm9_icache_sync_range (vaddr_t, vsize_t); - -void arm9_dcache_wbinv_all (void); -void arm9_dcache_wbinv_range (vaddr_t, vsize_t); -void arm9_dcache_inv_range (vaddr_t, vsize_t); -void arm9_dcache_wb_range (vaddr_t, vsize_t); - -void arm9_idcache_wbinv_all (void); -void arm9_idcache_wbinv_range (vaddr_t, vsize_t); - -void arm9_context_switch (u_int); - -void arm9_setup (void); - -extern unsigned arm9_dcache_sets_max; -extern unsigned arm9_dcache_sets_inc; -extern unsigned arm9_dcache_index_max; -extern unsigned arm9_dcache_index_inc; -#endif - #if defined(CPU_ARM9E) || defined(CPU_ARM10) void arm10_tlb_flushID_SE (u_int); void arm10_tlb_flushI_SE (u_int); @@ -377,7 +351,7 @@ extern unsigned armv7_dcache_index_inc; #endif -#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ +#if defined(CPU_ARM9E) || defined(CPU_ARM10) || \ defined(CPU_SA1100) || defined(CPU_SA1110) || \ defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) diff --git a/sys/arch/arm/include/pmap.h b/sys/arch/arm/include/pmap.h index 5461ee509ea..93a547008d7 100644 --- a/sys/arch/arm/include/pmap.h +++ b/sys/arch/arm/include/pmap.h @@ -1,4 +1,4 @@ -/* $OpenBSD: pmap.h,v 1.36 2016/03/18 06:54:21 jsg Exp $ */ +/* $OpenBSD: pmap.h,v 1.37 2016/03/18 13:16:02 jsg Exp $ */ /* $NetBSD: pmap.h,v 1.76 2003/09/06 09:10:46 rearnsha Exp $ */ /* @@ -371,9 +371,6 @@ void pmap_copy_page_generic(struct vm_page *, struct vm_page *); void pmap_zero_page_generic(struct vm_page *); void pmap_pte_init_generic(void); -#if defined(CPU_ARM9) -void pmap_pte_init_arm9(void); -#endif /* CPU_ARM9 */ #if defined(CPU_ARM10) void pmap_pte_init_arm10(void); #endif /* CPU_ARM10 */ |