diff options
| -rw-r--r-- | sys/dev/pci/pcidevs.h | 73 | ||||
| -rw-r--r-- | sys/dev/pci/pcidevs_data.h | 244 |
2 files changed, 301 insertions, 16 deletions
diff --git a/sys/dev/pci/pcidevs.h b/sys/dev/pci/pcidevs.h index ff0c0d4bcb5..40a9ad7c0f7 100644 --- a/sys/dev/pci/pcidevs.h +++ b/sys/dev/pci/pcidevs.h @@ -2,7 +2,7 @@ * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. * * generated from: - * OpenBSD: pcidevs,v 1.1934 2020/10/02 18:41:51 kettenis Exp + * OpenBSD: pcidevs,v 1.1935 2020/10/04 10:35:35 jsg Exp */ /* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */ @@ -3212,13 +3212,59 @@ #define PCI_PRODUCT_INTEL_CORE3G_D_GT2 0x0162 /* HD Graphics 4000 */ #define PCI_PRODUCT_INTEL_CORE3G_M_GT2 0x0166 /* HD Graphics 4000 */ #define PCI_PRODUCT_INTEL_CORE3G_S_GT2 0x016a /* HD Graphics P4000 */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_LPC_1 0x0284 /* 400 Series LPC */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_LPC_2 0x0285 /* 400 Series LPC */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_P2SB 0x02a0 /* 400 Series P2SB */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_PMC 0x02a1 /* 400 Series PMC */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_SMB 0x02a3 /* 400 Series SMBus */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_SPI_FLASH 0x02a4 /* 400 Series SPI */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_TH 0x02a6 /* 400 Series Trace Hub */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_UART_1 0x02a8 /* 400 Series UART */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_UART_2 0x02a9 /* 400 Series UART */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_SPI_1 0x02aa /* 400 Series SPI */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_SPI_2 0x02ab /* 400 Series SPI */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_9 0x02b0 /* 400 Series PCIE */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_10 0x02b1 /* 400 Series PCIE */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_11 0x02b2 /* 400 Series PCIE */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_12 0x02b3 /* 400 Series PCIE */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_13 0x02b4 /* 400 Series PCIE */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_14 0x02b5 /* 400 Series PCIE */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_15 0x02b6 /* 400 Series PCIE */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_16 0x02b7 /* 400 Series PCIE */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_1 0x02b8 /* 400 Series PCIE */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_2 0x02b9 /* 400 Series PCIE */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_3 0x02ba /* 400 Series PCIE */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_4 0x02bb /* 400 Series PCIE */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_5 0x02bc /* 400 Series PCIE */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_6 0x02bd /* 400 Series PCIE */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_7 0x02be /* 400 Series PCIE */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_8 0x02bf /* 400 Series PCIE */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_EMMC 0x02c4 /* 400 Series eMMC */ #define PCI_PRODUCT_INTEL_400SERIES_LP_I2C_1 0x02c5 /* 400 Series I2C */ #define PCI_PRODUCT_INTEL_400SERIES_LP_I2C_2 0x02c6 /* 400 Series I2C */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_UART_3 0x02c7 /* 400 Series UART */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_HDA 0x02c8 /* 400 Series HD Audio */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_AHCI 0x02d3 /* 400 Series AHCI */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_RAID_1 0x02d5 /* 400 Series RAID */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_RAID_2 0x02d7 /* 400 Series RAID */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_MEI_1 0x02e0 /* 400 Series MEI */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_MEI_2 0x02e1 /* 400 Series MEI */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_IDER 0x02e2 /* 400 Series IDE-R */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_KT 0x02e3 /* 400 Series KT */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_MEI_3 0x02e4 /* 400 Series MEI */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_MEI_4 0x02e5 /* 400 Series MEI */ #define PCI_PRODUCT_INTEL_400SERIES_LP_I2C_3 0x02e8 /* 400 Series I2C */ #define PCI_PRODUCT_INTEL_400SERIES_LP_I2C_4 0x02e9 /* 400 Series I2C */ #define PCI_PRODUCT_INTEL_400SERIES_LP_I2C_5 0x02ea /* 400 Series I2C */ #define PCI_PRODUCT_INTEL_400SERIES_LP_I2C_6 0x02eb /* 400 Series I2C */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_XHCI 0x02ed /* 400 Series xHCI */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_XDCI 0x02ee /* 400 Series xDCI */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_SRAM 0x02ef /* 400 Series Shared SRAM */ #define PCI_PRODUCT_INTEL_WL_22500_2 0x02f0 /* Wi-Fi 6 AX201 */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_SDXC 0x02f5 /* 400 Series SDXC */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_THERM 0x02f9 /* 400 Series Thermal */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_SPI_3 0x02fb /* 400 Series SPI */ +#define PCI_PRODUCT_INTEL_400SERIES_LP_ISH 0x02fc /* 400 Series ISH */ #define PCI_PRODUCT_INTEL_80303 0x0309 /* 80303 IOP */ #define PCI_PRODUCT_INTEL_80312 0x030d /* 80312 I/O Companion */ #define PCI_PRODUCT_INTEL_IOXAPIC_A 0x0326 /* IOxAPIC */ @@ -5377,13 +5423,24 @@ #define PCI_PRODUCT_INTEL_RCUXX 0x9622 /* RCUxx I2O RAID */ #define PCI_PRODUCT_INTEL_RCU31 0x9641 /* RCU31 I2O RAID */ #define PCI_PRODUCT_INTEL_RCU31L 0x96a1 /* RCU31L I2O RAID */ -#define PCI_PRODUCT_INTEL_CML_GT1_6 0x9ba5 /* UHD Graphics 610 */ -#define PCI_PRODUCT_INTEL_CML_GT1_7 0x9ba8 /* UHD Graphics 610 */ -#define PCI_PRODUCT_INTEL_CML_GT2_6 0x9bc5 /* UHD Graphics 630 */ -#define PCI_PRODUCT_INTEL_CML_GT2_7 0x9bc8 /* UHD Graphics 630 */ -#define PCI_PRODUCT_INTEL_CML_GT2_10 0x9bc6 /* UHD Graphics P630 */ -#define PCI_PRODUCT_INTEL_CML_GT2_11 0x9be6 /* UHD Graphics P630 */ -#define PCI_PRODUCT_INTEL_CML_GT2_12 0x9bf6 /* UHD Graphics P630 */ +#define PCI_PRODUCT_INTEL_CML_U_GT1_1 0x9b21 /* UHD Graphics */ +#define PCI_PRODUCT_INTEL_CML_U_GT2_1 0x9b41 /* UHD Graphics */ +#define PCI_PRODUCT_INTEL_CORE10G_U_HB 0x9b61 /* Core 10G Host */ +#define PCI_PRODUCT_INTEL_CML_GT1_4 0x9ba2 /* UHD Graphics */ +#define PCI_PRODUCT_INTEL_CML_GT1_3 0x9ba4 /* UHD Graphics */ +#define PCI_PRODUCT_INTEL_CML_GT1_1 0x9ba5 /* UHD Graphics 610 */ +#define PCI_PRODUCT_INTEL_CML_GT1_2 0x9ba8 /* UHD Graphics 610 */ +#define PCI_PRODUCT_INTEL_CML_U_GT1_2 0x9baa /* UHD Graphics */ +#define PCI_PRODUCT_INTEL_CML_U_GT1_3 0x9bac /* UHD Graphics */ +#define PCI_PRODUCT_INTEL_CML_GT2_4 0x9bc2 /* UHD Graphics */ +#define PCI_PRODUCT_INTEL_CML_GT2_3 0x9bc4 /* UHD Graphics */ +#define PCI_PRODUCT_INTEL_CML_GT2_1 0x9bc5 /* UHD Graphics 630 */ +#define PCI_PRODUCT_INTEL_CML_GT2_2 0x9bc8 /* UHD Graphics 630 */ +#define PCI_PRODUCT_INTEL_CML_GT2_5 0x9bc6 /* UHD Graphics P630 */ +#define PCI_PRODUCT_INTEL_CML_U_GT2_2 0x9bca /* UHD Graphics */ +#define PCI_PRODUCT_INTEL_CML_U_GT2_3 0x9bcc /* UHD Graphics */ +#define PCI_PRODUCT_INTEL_CML_GT2_6 0x9be6 /* UHD Graphics P630 */ +#define PCI_PRODUCT_INTEL_CML_GT2_7 0x9bf6 /* UHD Graphics P630 */ #define PCI_PRODUCT_INTEL_8SERIES_LP_SATA_1 0x9c00 /* 8 Series SATA */ #define PCI_PRODUCT_INTEL_8SERIES_LP_SATA_2 0x9c01 /* 8 Series SATA */ #define PCI_PRODUCT_INTEL_8SERIES_LP_AHCI 0x9c03 /* 8 Series AHCI */ diff --git a/sys/dev/pci/pcidevs_data.h b/sys/dev/pci/pcidevs_data.h index c439f277169..d9086172f26 100644 --- a/sys/dev/pci/pcidevs_data.h +++ b/sys/dev/pci/pcidevs_data.h @@ -2,7 +2,7 @@ * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. * * generated from: - * OpenBSD: pcidevs,v 1.1934 2020/10/02 18:41:51 kettenis Exp + * OpenBSD: pcidevs,v 1.1935 2020/10/04 10:35:35 jsg Exp */ /* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */ @@ -10280,6 +10280,118 @@ static const struct pci_known_product pci_known_products[] = { "HD Graphics P4000", }, { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_LPC_1, + "400 Series LPC", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_LPC_2, + "400 Series LPC", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_P2SB, + "400 Series P2SB", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_PMC, + "400 Series PMC", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_SMB, + "400 Series SMBus", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_SPI_FLASH, + "400 Series SPI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_TH, + "400 Series Trace Hub", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_UART_1, + "400 Series UART", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_UART_2, + "400 Series UART", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_SPI_1, + "400 Series SPI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_SPI_2, + "400 Series SPI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_9, + "400 Series PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_10, + "400 Series PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_11, + "400 Series PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_12, + "400 Series PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_13, + "400 Series PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_14, + "400 Series PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_15, + "400 Series PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_16, + "400 Series PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_1, + "400 Series PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_2, + "400 Series PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_3, + "400 Series PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_4, + "400 Series PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_5, + "400 Series PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_6, + "400 Series PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_7, + "400 Series PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_PCIE_8, + "400 Series PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_EMMC, + "400 Series eMMC", + }, + { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_1, "400 Series I2C", }, @@ -10288,6 +10400,50 @@ static const struct pci_known_product pci_known_products[] = { "400 Series I2C", }, { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_UART_3, + "400 Series UART", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_HDA, + "400 Series HD Audio", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_AHCI, + "400 Series AHCI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_RAID_1, + "400 Series RAID", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_RAID_2, + "400 Series RAID", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_MEI_1, + "400 Series MEI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_MEI_2, + "400 Series MEI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_IDER, + "400 Series IDE-R", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_KT, + "400 Series KT", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_MEI_3, + "400 Series MEI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_MEI_4, + "400 Series MEI", + }, + { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_3, "400 Series I2C", }, @@ -10304,10 +10460,38 @@ static const struct pci_known_product pci_known_products[] = { "400 Series I2C", }, { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_XHCI, + "400 Series xHCI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_XDCI, + "400 Series xDCI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_SRAM, + "400 Series Shared SRAM", + }, + { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_22500_2, "Wi-Fi 6 AX201", }, { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_SDXC, + "400 Series SDXC", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_THERM, + "400 Series Thermal", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_SPI_3, + "400 Series SPI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_ISH, + "400 Series ISH", + }, + { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80303, "80303 IOP", }, @@ -18940,31 +19124,75 @@ static const struct pci_known_product pci_known_products[] = { "RCU31L I2O RAID", }, { - PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_GT1_6, + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_U_GT1_1, + "UHD Graphics", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_U_GT2_1, + "UHD Graphics", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE10G_U_HB, + "Core 10G Host", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_GT1_4, + "UHD Graphics", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_GT1_3, + "UHD Graphics", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_GT1_1, "UHD Graphics 610", }, { - PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_GT1_7, + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_GT1_2, "UHD Graphics 610", }, { - PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_GT2_6, + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_U_GT1_2, + "UHD Graphics", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_U_GT1_3, + "UHD Graphics", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_GT2_4, + "UHD Graphics", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_GT2_3, + "UHD Graphics", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_GT2_1, "UHD Graphics 630", }, { - PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_GT2_7, + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_GT2_2, "UHD Graphics 630", }, { - PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_GT2_10, + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_GT2_5, "UHD Graphics P630", }, { - PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_GT2_11, + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_U_GT2_2, + "UHD Graphics", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_U_GT2_3, + "UHD Graphics", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_GT2_6, "UHD Graphics P630", }, { - PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_GT2_12, + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CML_GT2_7, "UHD Graphics P630", }, { |