diff options
Diffstat (limited to 'gnu/llvm/lib/CodeGen/MIRPrinter.cpp')
| -rw-r--r-- | gnu/llvm/lib/CodeGen/MIRPrinter.cpp | 532 |
1 files changed, 114 insertions, 418 deletions
diff --git a/gnu/llvm/lib/CodeGen/MIRPrinter.cpp b/gnu/llvm/lib/CodeGen/MIRPrinter.cpp index ddeacf1d1bf..f91cca6e4e5 100644 --- a/gnu/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/gnu/llvm/lib/CodeGen/MIRPrinter.cpp @@ -12,16 +12,18 @@ // //===----------------------------------------------------------------------===// +#include "llvm/CodeGen/MIRPrinter.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/None.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallBitVector.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" -#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/Twine.h" #include "llvm/CodeGen/GlobalISel/RegisterBank.h" +#include "llvm/CodeGen/MIRYamlMapping.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -31,19 +33,20 @@ #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/MIRPrinter.h" -#include "llvm/CodeGen/MIRYamlMapping.h" #include "llvm/CodeGen/PseudoSourceValue.h" +#include "llvm/CodeGen/TargetInstrInfo.h" +#include "llvm/CodeGen/TargetRegisterInfo.h" +#include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/IR/BasicBlock.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DebugInfo.h" #include "llvm/IR/DebugLoc.h" #include "llvm/IR/Function.h" #include "llvm/IR/GlobalValue.h" +#include "llvm/IR/IRPrintingPasses.h" #include "llvm/IR/InstrTypes.h" #include "llvm/IR/Instructions.h" #include "llvm/IR/Intrinsics.h" -#include "llvm/IR/IRPrintingPasses.h" #include "llvm/IR/Module.h" #include "llvm/IR/ModuleSlotTracker.h" #include "llvm/IR/Value.h" @@ -57,13 +60,10 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Format.h" #include "llvm/Support/LowLevelTypeImpl.h" -#include "llvm/Support/raw_ostream.h" #include "llvm/Support/YAMLTraits.h" -#include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetIntrinsicInfo.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetRegisterInfo.h" -#include "llvm/Target/TargetSubtargetInfo.h" #include <algorithm> #include <cassert> #include <cinttypes> @@ -75,7 +75,8 @@ using namespace llvm; -static cl::opt<bool> SimplifyMIR("simplify-mir", +static cl::opt<bool> SimplifyMIR( + "simplify-mir", cl::Hidden, cl::desc("Leave out unnecessary information when printing MIR")); namespace { @@ -156,20 +157,14 @@ public: void print(const MachineBasicBlock &MBB); void print(const MachineInstr &MI); - void printMBBReference(const MachineBasicBlock &MBB); - void printIRBlockReference(const BasicBlock &BB); void printIRValueReference(const Value &V); void printStackObjectReference(int FrameIndex); - void printOffset(int64_t Offset); - void printTargetFlags(const MachineOperand &Op); - void print(const MachineOperand &Op, const TargetRegisterInfo *TRI, - unsigned I, bool ShouldPrintRegisterTies, - LLT TypeToPrint, bool IsDef = false); + void print(const MachineInstr &MI, unsigned OpIdx, + const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies, + LLT TypeToPrint, bool PrintDef = true); void print(const LLVMContext &Context, const TargetInstrInfo &TII, const MachineMemOperand &Op); void printSyncScope(const LLVMContext &Context, SyncScope::ID SSID); - - void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI); }; } // end namespace llvm @@ -192,23 +187,10 @@ template <> struct BlockScalarTraits<Module> { } // end namespace yaml } // end namespace llvm -static void printReg(unsigned Reg, raw_ostream &OS, - const TargetRegisterInfo *TRI) { - // TODO: Print Stack Slots. - if (!Reg) - OS << '_'; - else if (TargetRegisterInfo::isVirtualRegister(Reg)) - OS << '%' << TargetRegisterInfo::virtReg2Index(Reg); - else if (Reg < TRI->getNumRegs()) - OS << '%' << StringRef(TRI->getName(Reg)).lower(); - else - llvm_unreachable("Can't print this kind of register yet"); -} - -static void printReg(unsigned Reg, yaml::StringValue &Dest, - const TargetRegisterInfo *TRI) { +static void printRegMIR(unsigned Reg, yaml::StringValue &Dest, + const TargetRegisterInfo *TRI) { raw_string_ostream OS(Dest.Value); - printReg(Reg, OS, TRI); + OS << printReg(Reg, TRI); } void MIRPrinter::print(const MachineFunction &MF) { @@ -227,8 +209,8 @@ void MIRPrinter::print(const MachineFunction &MF) { MachineFunctionProperties::Property::Selected); convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo()); - ModuleSlotTracker MST(MF.getFunction()->getParent()); - MST.incorporateFunction(*MF.getFunction()); + ModuleSlotTracker MST(MF.getFunction().getParent()); + MST.incorporateFunction(MF.getFunction()); convert(MST, YamlMF.FrameInfo, MF.getFrameInfo()); convertStackObjects(YamlMF, MF, MST); if (const auto *ConstantPool = MF.getConstantPool()) @@ -262,7 +244,7 @@ static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS, if (RegMask[I / 32] & (1u << (I % 32))) { if (IsRegInRegMaskFound) OS << ','; - printReg(I, OS, TRI); + OS << printReg(I, TRI); IsRegInRegMaskFound = true; } } @@ -270,6 +252,14 @@ static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS, OS << ')'; } +static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest, + const MachineRegisterInfo &RegInfo, + const TargetRegisterInfo *TRI) { + raw_string_ostream OS(Dest.Value); + OS << printRegClassOrBank(Reg, RegInfo, TRI); +} + + void MIRPrinter::convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI) { @@ -280,28 +270,19 @@ void MIRPrinter::convert(yaml::MachineFunction &MF, unsigned Reg = TargetRegisterInfo::index2VirtReg(I); yaml::VirtualRegisterDefinition VReg; VReg.ID = I; - if (RegInfo.getRegClassOrNull(Reg)) - VReg.Class = - StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); - else if (RegInfo.getRegBankOrNull(Reg)) - VReg.Class = StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower(); - else { - VReg.Class = std::string("_"); - assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) && - "Generic registers must have a valid type"); - } + ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI); unsigned PreferredReg = RegInfo.getSimpleHint(Reg); if (PreferredReg) - printReg(PreferredReg, VReg.PreferredRegister, TRI); + printRegMIR(PreferredReg, VReg.PreferredRegister, TRI); MF.VirtualRegisters.push_back(VReg); } // Print the live ins. - for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) { + for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) { yaml::MachineFunctionLiveIn LiveIn; - printReg(I->first, LiveIn.Register, TRI); - if (I->second) - printReg(I->second, LiveIn.VirtualRegister, TRI); + printRegMIR(LI.first, LiveIn.Register, TRI); + if (LI.second) + printRegMIR(LI.second, LiveIn.VirtualRegister, TRI); MF.LiveIns.push_back(LiveIn); } @@ -311,7 +292,7 @@ void MIRPrinter::convert(yaml::MachineFunction &MF, std::vector<yaml::FlowStringValue> CalleeSavedRegisters; for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) { yaml::FlowStringValue Reg; - printReg(*I, Reg, TRI); + printRegMIR(*I, Reg, TRI); CalleeSavedRegisters.push_back(Reg); } MF.CalleeSavedRegisters = CalleeSavedRegisters; @@ -337,13 +318,11 @@ void MIRPrinter::convert(ModuleSlotTracker &MST, YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc(); if (MFI.getSavePoint()) { raw_string_ostream StrOS(YamlMFI.SavePoint.Value); - MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping) - .printMBBReference(*MFI.getSavePoint()); + StrOS << printMBBReference(*MFI.getSavePoint()); } if (MFI.getRestorePoint()) { raw_string_ostream StrOS(YamlMFI.RestorePoint.Value); - MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping) - .printMBBReference(*MFI.getRestorePoint()); + StrOS << printMBBReference(*MFI.getRestorePoint()); } } @@ -366,6 +345,7 @@ void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF, YamlObject.Offset = MFI.getObjectOffset(I); YamlObject.Size = MFI.getObjectSize(I); YamlObject.Alignment = MFI.getObjectAlignment(I); + YamlObject.StackID = MFI.getStackID(I); YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I); YamlObject.IsAliased = MFI.isAliasedObjectIndex(I); YMF.FixedStackObjects.push_back(YamlObject); @@ -392,6 +372,7 @@ void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF, YamlObject.Offset = MFI.getObjectOffset(I); YamlObject.Size = MFI.getObjectSize(I); YamlObject.Alignment = MFI.getObjectAlignment(I); + YamlObject.StackID = MFI.getStackID(I); YMF.StackObjects.push_back(YamlObject); StackObjectOperandMapping.insert(std::make_pair( @@ -400,15 +381,20 @@ void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF, for (const auto &CSInfo : MFI.getCalleeSavedInfo()) { yaml::StringValue Reg; - printReg(CSInfo.getReg(), Reg, TRI); + printRegMIR(CSInfo.getReg(), Reg, TRI); auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx()); assert(StackObjectInfo != StackObjectOperandMapping.end() && "Invalid stack object index"); const FrameIndexOperand &StackObject = StackObjectInfo->second; - if (StackObject.IsFixed) + if (StackObject.IsFixed) { YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg; - else + YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored = + CSInfo.isRestored(); + } else { YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg; + YMF.StackObjects[StackObject.ID].CalleeSavedRestored = + CSInfo.isRestored(); + } } for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) { auto LocalObject = MFI.getLocalFrameObjectMap(I); @@ -456,17 +442,20 @@ void MIRPrinter::convert(yaml::MachineFunction &MF, const MachineConstantPool &ConstantPool) { unsigned ID = 0; for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) { - // TODO: Serialize target specific constant pool entries. - if (Constant.isMachineConstantPoolEntry()) - llvm_unreachable("Can't print target specific constant pool entries yet"); - - yaml::MachineConstantPoolValue YamlConstant; std::string Str; raw_string_ostream StrOS(Str); - Constant.Val.ConstVal->printAsOperand(StrOS); + if (Constant.isMachineConstantPoolEntry()) { + Constant.Val.MachineCPVal->print(StrOS); + } else { + Constant.Val.ConstVal->printAsOperand(StrOS); + } + + yaml::MachineConstantPoolValue YamlConstant; YamlConstant.ID = ID++; YamlConstant.Value = StrOS.str(); YamlConstant.Alignment = Constant.getAlignment(); + YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry(); + MF.Constants.push_back(YamlConstant); } } @@ -482,8 +471,7 @@ void MIRPrinter::convert(ModuleSlotTracker &MST, Entry.ID = ID++; for (const auto *MBB : Table.MBBs) { raw_string_ostream StrOS(Str); - MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping) - .printMBBReference(*MBB); + StrOS << printMBBReference(*MBB); Entry.Blocks.push_back(StrOS.str()); Str.clear(); } @@ -593,13 +581,19 @@ void MIPrinter::print(const MachineBasicBlock &MBB) { bool HasLineAttributes = false; // Print the successors bool canPredictProbs = canPredictBranchProbabilities(MBB); - if (!MBB.succ_empty() && (!SimplifyMIR || !canPredictProbs || - !canPredictSuccessors(MBB))) { + // Even if the list of successors is empty, if we cannot guess it, + // we need to print it to tell the parser that the list is empty. + // This is needed, because MI model unreachable as empty blocks + // with an empty successor list. If the parser would see that + // without the successor list, it would guess the code would + // fallthrough. + if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs || + !canPredictSuccessors(MBB)) { OS.indent(2) << "successors: "; for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) { if (I != MBB.succ_begin()) OS << ", "; - printMBBReference(**I); + OS << printMBBReference(**I); if (!SimplifyMIR || !canPredictProbs) OS << '(' << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator()) @@ -619,7 +613,7 @@ void MIPrinter::print(const MachineBasicBlock &MBB) { if (!First) OS << ", "; First = false; - printReg(LI.PhysReg, OS, &TRI); + OS << printReg(LI.PhysReg, &TRI); if (!LI.LaneMask.all()) OS << ":0x" << PrintLaneMask(LI.LaneMask); } @@ -648,46 +642,8 @@ void MIPrinter::print(const MachineBasicBlock &MBB) { OS.indent(2) << "}\n"; } -/// Return true when an instruction has tied register that can't be determined -/// by the instruction's descriptor. -static bool hasComplexRegisterTies(const MachineInstr &MI) { - const MCInstrDesc &MCID = MI.getDesc(); - for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) { - const auto &Operand = MI.getOperand(I); - if (!Operand.isReg() || Operand.isDef()) - // Ignore the defined registers as MCID marks only the uses as tied. - continue; - int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO); - int TiedIdx = Operand.isTied() ? int(MI.findTiedOperandIdx(I)) : -1; - if (ExpectedTiedIdx != TiedIdx) - return true; - } - return false; -} - -static LLT getTypeToPrint(const MachineInstr &MI, unsigned OpIdx, - SmallBitVector &PrintedTypes, - const MachineRegisterInfo &MRI) { - const MachineOperand &Op = MI.getOperand(OpIdx); - if (!Op.isReg()) - return LLT{}; - - if (MI.isVariadic() || OpIdx >= MI.getNumExplicitOperands()) - return MRI.getType(Op.getReg()); - - auto &OpInfo = MI.getDesc().OpInfo[OpIdx]; - if (!OpInfo.isGenericType()) - return MRI.getType(Op.getReg()); - - if (PrintedTypes[OpInfo.getGenericTypeIndex()]) - return LLT{}; - - PrintedTypes.set(OpInfo.getGenericTypeIndex()); - return MRI.getType(Op.getReg()); -} - void MIPrinter::print(const MachineInstr &MI) { - const auto *MF = MI.getParent()->getParent(); + const auto *MF = MI.getMF(); const auto &MRI = MF->getRegInfo(); const auto &SubTarget = MF->getSubtarget(); const auto *TRI = SubTarget.getRegisterInfo(); @@ -698,16 +654,16 @@ void MIPrinter::print(const MachineInstr &MI) { assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction"); SmallBitVector PrintedTypes(8); - bool ShouldPrintRegisterTies = hasComplexRegisterTies(MI); + bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies(); unsigned I = 0, E = MI.getNumOperands(); for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() && !MI.getOperand(I).isImplicit(); ++I) { if (I) OS << ", "; - print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies, - getTypeToPrint(MI, I, PrintedTypes, MRI), - /*IsDef=*/true); + print(MI, I, TRI, ShouldPrintRegisterTies, + MI.getTypeToPrint(I, PrintedTypes, MRI), + /*PrintDef=*/false); } if (I) @@ -722,8 +678,8 @@ void MIPrinter::print(const MachineInstr &MI) { for (; I < E; ++I) { if (NeedComma) OS << ", "; - print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies, - getTypeToPrint(MI, I, PrintedTypes, MRI)); + print(MI, I, TRI, ShouldPrintRegisterTies, + MI.getTypeToPrint(I, PrintedTypes, MRI)); NeedComma = true; } @@ -736,7 +692,7 @@ void MIPrinter::print(const MachineInstr &MI) { if (!MI.memoperands_empty()) { OS << " :: "; - const LLVMContext &Context = MF->getFunction()->getContext(); + const LLVMContext &Context = MF->getFunction().getContext(); bool NeedComma = false; for (const auto *Op : MI.memoperands()) { if (NeedComma) @@ -747,40 +703,6 @@ void MIPrinter::print(const MachineInstr &MI) { } } -void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) { - OS << "%bb." << MBB.getNumber(); - if (const auto *BB = MBB.getBasicBlock()) { - if (BB->hasName()) - OS << '.' << BB->getName(); - } -} - -static void printIRSlotNumber(raw_ostream &OS, int Slot) { - if (Slot == -1) - OS << "<badref>"; - else - OS << Slot; -} - -void MIPrinter::printIRBlockReference(const BasicBlock &BB) { - OS << "%ir-block."; - if (BB.hasName()) { - printLLVMNameWithoutPrefix(OS, BB.getName()); - return; - } - const Function *F = BB.getParent(); - int Slot; - if (F == MST.getCurrentFunction()) { - Slot = MST.getLocalSlot(&BB); - } else { - ModuleSlotTracker CustomMST(F->getParent(), - /*ShouldInitializeAllMetadata=*/false); - CustomMST.incorporateFunction(*F); - Slot = CustomMST.getLocalSlot(&BB); - } - printIRSlotNumber(OS, Slot); -} - void MIPrinter::printIRValueReference(const Value &V) { if (isa<GlobalValue>(V)) { V.printAsOperand(OS, /*PrintType=*/false, MST); @@ -798,7 +720,7 @@ void MIPrinter::printIRValueReference(const Value &V) { printLLVMNameWithoutPrefix(OS, V.getName()); return; } - printIRSlotNumber(OS, MST.getLocalSlot(&V)); + MachineOperand::printIRSlotNumber(OS, MST.getLocalSlot(&V)); } void MIPrinter::printStackObjectReference(int FrameIndex) { @@ -806,182 +728,49 @@ void MIPrinter::printStackObjectReference(int FrameIndex) { assert(ObjectInfo != StackObjectOperandMapping.end() && "Invalid frame index"); const FrameIndexOperand &Operand = ObjectInfo->second; - if (Operand.IsFixed) { - OS << "%fixed-stack." << Operand.ID; - return; - } - OS << "%stack." << Operand.ID; - if (!Operand.Name.empty()) - OS << '.' << Operand.Name; -} - -void MIPrinter::printOffset(int64_t Offset) { - if (Offset == 0) - return; - if (Offset < 0) { - OS << " - " << -Offset; - return; - } - OS << " + " << Offset; -} - -static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) { - auto Flags = TII->getSerializableDirectMachineOperandTargetFlags(); - for (const auto &I : Flags) { - if (I.first == TF) { - return I.second; - } - } - return nullptr; -} - -void MIPrinter::printTargetFlags(const MachineOperand &Op) { - if (!Op.getTargetFlags()) - return; - const auto *TII = - Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo(); - assert(TII && "expected instruction info"); - auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags()); - OS << "target-flags("; - const bool HasDirectFlags = Flags.first; - const bool HasBitmaskFlags = Flags.second; - if (!HasDirectFlags && !HasBitmaskFlags) { - OS << "<unknown>) "; - return; - } - if (HasDirectFlags) { - if (const auto *Name = getTargetFlagName(TII, Flags.first)) - OS << Name; - else - OS << "<unknown target flag>"; - } - if (!HasBitmaskFlags) { - OS << ") "; - return; - } - bool IsCommaNeeded = HasDirectFlags; - unsigned BitMask = Flags.second; - auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags(); - for (const auto &Mask : BitMasks) { - // Check if the flag's bitmask has the bits of the current mask set. - if ((BitMask & Mask.first) == Mask.first) { - if (IsCommaNeeded) - OS << ", "; - IsCommaNeeded = true; - OS << Mask.second; - // Clear the bits which were serialized from the flag's bitmask. - BitMask &= ~(Mask.first); - } - } - if (BitMask) { - // When the resulting flag's bitmask isn't zero, we know that we didn't - // serialize all of the bit flags. - if (IsCommaNeeded) - OS << ", "; - OS << "<unknown bitmask target flag>"; - } - OS << ") "; + MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed, + Operand.Name); } -static const char *getTargetIndexName(const MachineFunction &MF, int Index) { - const auto *TII = MF.getSubtarget().getInstrInfo(); - assert(TII && "expected instruction info"); - auto Indices = TII->getSerializableTargetIndices(); - for (const auto &I : Indices) { - if (I.first == Index) { - return I.second; - } - } - return nullptr; -} - -void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI, - unsigned I, bool ShouldPrintRegisterTies, LLT TypeToPrint, - bool IsDef) { - printTargetFlags(Op); +void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx, + const TargetRegisterInfo *TRI, + bool ShouldPrintRegisterTies, LLT TypeToPrint, + bool PrintDef) { + const MachineOperand &Op = MI.getOperand(OpIdx); switch (Op.getType()) { - case MachineOperand::MO_Register: - if (Op.isImplicit()) - OS << (Op.isDef() ? "implicit-def " : "implicit "); - else if (!IsDef && Op.isDef()) - // Print the 'def' flag only when the operand is defined after '='. - OS << "def "; - if (Op.isInternalRead()) - OS << "internal "; - if (Op.isDead()) - OS << "dead "; - if (Op.isKill()) - OS << "killed "; - if (Op.isUndef()) - OS << "undef "; - if (Op.isEarlyClobber()) - OS << "early-clobber "; - if (Op.isDebug()) - OS << "debug-use "; - printReg(Op.getReg(), OS, TRI); - // Print the sub register. - if (Op.getSubReg() != 0) - OS << '.' << TRI->getSubRegIndexName(Op.getSubReg()); - if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef()) - OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(I) << ")"; - if (TypeToPrint.isValid()) - OS << '(' << TypeToPrint << ')'; - break; case MachineOperand::MO_Immediate: - OS << Op.getImm(); - break; + if (MI.isOperandSubregIdx(OpIdx)) { + MachineOperand::printTargetFlags(OS, Op); + MachineOperand::printSubregIdx(OS, Op.getImm(), TRI); + break; + } + LLVM_FALLTHROUGH; + case MachineOperand::MO_Register: case MachineOperand::MO_CImmediate: - Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST); - break; case MachineOperand::MO_FPImmediate: - Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST); - break; case MachineOperand::MO_MachineBasicBlock: - printMBBReference(*Op.getMBB()); - break; - case MachineOperand::MO_FrameIndex: - printStackObjectReference(Op.getIndex()); - break; case MachineOperand::MO_ConstantPoolIndex: - OS << "%const." << Op.getIndex(); - printOffset(Op.getOffset()); - break; case MachineOperand::MO_TargetIndex: - OS << "target-index("; - if (const auto *Name = getTargetIndexName( - *Op.getParent()->getParent()->getParent(), Op.getIndex())) - OS << Name; - else - OS << "<unknown>"; - OS << ')'; - printOffset(Op.getOffset()); - break; case MachineOperand::MO_JumpTableIndex: - OS << "%jump-table." << Op.getIndex(); - break; - case MachineOperand::MO_ExternalSymbol: { - StringRef Name = Op.getSymbolName(); - OS << '$'; - if (Name.empty()) { - OS << "\"\""; - } else { - printLLVMNameWithoutPrefix(OS, Name); - } - printOffset(Op.getOffset()); - break; - } + case MachineOperand::MO_ExternalSymbol: case MachineOperand::MO_GlobalAddress: - Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST); - printOffset(Op.getOffset()); + case MachineOperand::MO_RegisterLiveOut: + case MachineOperand::MO_Metadata: + case MachineOperand::MO_MCSymbol: + case MachineOperand::MO_CFIIndex: + case MachineOperand::MO_IntrinsicID: + case MachineOperand::MO_Predicate: + case MachineOperand::MO_BlockAddress: { + unsigned TiedOperandIdx = 0; + if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef()) + TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx); + const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo(); + Op.print(OS, MST, TypeToPrint, PrintDef, ShouldPrintRegisterTies, + TiedOperandIdx, TRI, TII); break; - case MachineOperand::MO_BlockAddress: - OS << "blockaddress("; - Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false, - MST); - OS << ", "; - printIRBlockReference(*Op.getBlockAddress()->getBasicBlock()); - OS << ')'; - printOffset(Op.getOffset()); + } + case MachineOperand::MO_FrameIndex: + printStackObjectReference(Op.getIndex()); break; case MachineOperand::MO_RegisterMask: { auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask()); @@ -991,49 +780,6 @@ void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI, printCustomRegMask(Op.getRegMask(), OS, TRI); break; } - case MachineOperand::MO_RegisterLiveOut: { - const uint32_t *RegMask = Op.getRegLiveOut(); - OS << "liveout("; - bool IsCommaNeeded = false; - for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) { - if (RegMask[Reg / 32] & (1U << (Reg % 32))) { - if (IsCommaNeeded) - OS << ", "; - printReg(Reg, OS, TRI); - IsCommaNeeded = true; - } - } - OS << ")"; - break; - } - case MachineOperand::MO_Metadata: - Op.getMetadata()->printAsOperand(OS, MST); - break; - case MachineOperand::MO_MCSymbol: - OS << "<mcsymbol " << *Op.getMCSymbol() << ">"; - break; - case MachineOperand::MO_CFIIndex: { - const MachineFunction &MF = *Op.getParent()->getParent()->getParent(); - print(MF.getFrameInstructions()[Op.getCFIIndex()], TRI); - break; - } - case MachineOperand::MO_IntrinsicID: { - Intrinsic::ID ID = Op.getIntrinsicID(); - if (ID < Intrinsic::num_intrinsics) - OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')'; - else { - const MachineFunction &MF = *Op.getParent()->getParent()->getParent(); - const TargetIntrinsicInfo *TII = MF.getTarget().getIntrinsicInfo(); - OS << "intrinsic(@" << TII->getName(ID) << ')'; - } - break; - } - case MachineOperand::MO_Predicate: { - auto Pred = static_cast<CmpInst::Predicate>(Op.getPredicate()); - OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred(" - << CmpInst::getPredicateName(Pred) << ')'; - break; - } } } @@ -1068,12 +814,12 @@ void MIPrinter::print(const LLVMContext &Context, const TargetInstrInfo &TII, if (Op.getFlags() & MachineMemOperand::MOTargetFlag3) OS << '"' << getTargetMMOFlagName(TII, MachineMemOperand::MOTargetFlag3) << "\" "; + + assert((Op.isLoad() || Op.isStore()) && "machine memory operand must be a load or store (or both)"); if (Op.isLoad()) OS << "load "; - else { - assert(Op.isStore() && "Non load machine operand must be a store"); + if (Op.isStore()) OS << "store "; - } printSyncScope(Context, Op.getSyncScopeID()); @@ -1084,10 +830,12 @@ void MIPrinter::print(const LLVMContext &Context, const TargetInstrInfo &TII, OS << Op.getSize(); if (const Value *Val = Op.getValue()) { - OS << (Op.isLoad() ? " from " : " into "); + OS << ((Op.isLoad() && Op.isStore()) ? " on " + : Op.isLoad() ? " from " : " into "); printIRValueReference(*Val); } else if (const PseudoSourceValue *PVal = Op.getPseudoValue()) { - OS << (Op.isLoad() ? " from " : " into "); + OS << ((Op.isLoad() && Op.isStore()) ? " on " + : Op.isLoad() ? " from " : " into "); assert(PVal && "Expected a pseudo source value"); switch (PVal->kind()) { case PseudoSourceValue::Stack: @@ -1121,7 +869,7 @@ void MIPrinter::print(const LLVMContext &Context, const TargetInstrInfo &TII, break; } } - printOffset(Op.getOffset()); + MachineOperand::printOperandOffset(OS, Op.getOffset()); if (Op.getBaseAlignment() != Op.getSize()) OS << ", align " << Op.getBaseAlignment(); auto AAInfo = Op.getAAInfo(); @@ -1161,58 +909,6 @@ void MIPrinter::printSyncScope(const LLVMContext &Context, SyncScope::ID SSID) { } } -static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, - const TargetRegisterInfo *TRI) { - int Reg = TRI->getLLVMRegNum(DwarfReg, true); - if (Reg == -1) { - OS << "<badreg>"; - return; - } - printReg(Reg, OS, TRI); -} - -void MIPrinter::print(const MCCFIInstruction &CFI, - const TargetRegisterInfo *TRI) { - switch (CFI.getOperation()) { - case MCCFIInstruction::OpSameValue: - OS << "same_value "; - if (CFI.getLabel()) - OS << "<mcsymbol> "; - printCFIRegister(CFI.getRegister(), OS, TRI); - break; - case MCCFIInstruction::OpOffset: - OS << "offset "; - if (CFI.getLabel()) - OS << "<mcsymbol> "; - printCFIRegister(CFI.getRegister(), OS, TRI); - OS << ", " << CFI.getOffset(); - break; - case MCCFIInstruction::OpDefCfaRegister: - OS << "def_cfa_register "; - if (CFI.getLabel()) - OS << "<mcsymbol> "; - printCFIRegister(CFI.getRegister(), OS, TRI); - break; - case MCCFIInstruction::OpDefCfaOffset: - OS << "def_cfa_offset "; - if (CFI.getLabel()) - OS << "<mcsymbol> "; - OS << CFI.getOffset(); - break; - case MCCFIInstruction::OpDefCfa: - OS << "def_cfa "; - if (CFI.getLabel()) - OS << "<mcsymbol> "; - printCFIRegister(CFI.getRegister(), OS, TRI); - OS << ", " << CFI.getOffset(); - break; - default: - // TODO: Print the other CFI Operations. - OS << "<unserializable cfi operation>"; - break; - } -} - void llvm::printMIR(raw_ostream &OS, const Module &M) { yaml::Output Out(OS); Out << const_cast<Module &>(M); |