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-rw-r--r--gnu/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp103
1 files changed, 64 insertions, 39 deletions
diff --git a/gnu/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/gnu/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 376727729d8..b14b2c6a813 100644
--- a/gnu/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/gnu/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -24,13 +24,6 @@
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineInstrBundle.h"
-#include "llvm/IR/GlobalValue.h"
-#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
-#include "llvm/Target/TargetFrameLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
@@ -40,6 +33,8 @@ static cl::opt<bool>
VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
cl::desc("Verify machine code after expanding ARM pseudos"));
+#define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
+
namespace {
class ARMExpandPseudo : public MachineFunctionPass {
public:
@@ -59,7 +54,7 @@ namespace {
}
StringRef getPassName() const override {
- return "ARM pseudo instruction expansion pass";
+ return ARM_EXPAND_PSEUDO_NAME;
}
private:
@@ -88,6 +83,9 @@ namespace {
char ARMExpandPseudo::ID = 0;
}
+INITIALIZE_PASS(ARMExpandPseudo, DEBUG_TYPE, ARM_EXPAND_PSEUDO_NAME, false,
+ false)
+
/// TransferImpOps - Transfer implicit operands on the pseudo instruction to
/// the instructions created from the expansion.
void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
@@ -608,8 +606,11 @@ void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
// Transfer the destination register operand.
MIB.add(MI.getOperand(OpIdx++));
- if (IsExt)
- MIB.add(MI.getOperand(OpIdx++));
+ if (IsExt) {
+ MachineOperand VdSrc(MI.getOperand(OpIdx++));
+ VdSrc.setIsRenamable(false);
+ MIB.add(VdSrc);
+ }
bool SrcIsKill = MI.getOperand(OpIdx).isKill();
unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
@@ -618,7 +619,9 @@ void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
MIB.addReg(D0);
// Copy the other source register operand.
- MIB.add(MI.getOperand(OpIdx++));
+ MachineOperand VmSrc(MI.getOperand(OpIdx++));
+ VmSrc.setIsRenamable(false);
+ MIB.add(VmSrc);
// Copy the predicate operands.
MIB.add(MI.getOperand(OpIdx++));
@@ -666,6 +669,12 @@ static bool IsAnAddressOperand(const MachineOperand &MO) {
llvm_unreachable("unhandled machine operand type");
}
+static MachineOperand makeImplicit(const MachineOperand &MO) {
+ MachineOperand NewMO = MO;
+ NewMO.setImplicit();
+ return NewMO;
+}
+
void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI) {
MachineInstr &MI = *MBBI;
@@ -700,6 +709,8 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
LO16.addImm(Pred).addReg(PredReg).add(condCodeOp());
HI16.addImm(Pred).addReg(PredReg).add(condCodeOp());
+ if (isCC)
+ LO16.add(makeImplicit(MI.getOperand(1)));
TransferImpOps(MI, LO16, HI16);
MI.eraseFromParent();
return;
@@ -753,6 +764,8 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
if (RequiresBundling)
finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator());
+ if (isCC)
+ LO16.add(makeImplicit(MI.getOperand(1)));
TransferImpOps(MI, LO16, HI16);
MI.eraseFromParent();
}
@@ -852,16 +865,15 @@ bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
MI.eraseFromParent();
// Recompute livein lists.
- const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
LivePhysRegs LiveRegs;
- computeLiveIns(LiveRegs, MRI, *DoneBB);
- computeLiveIns(LiveRegs, MRI, *StoreBB);
- computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
+ computeAndAddLiveIns(LiveRegs, *DoneBB);
+ computeAndAddLiveIns(LiveRegs, *StoreBB);
+ computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
// Do an extra pass around the loop to get loop carried registers right.
StoreBB->clearLiveIns();
- computeLiveIns(LiveRegs, MRI, *StoreBB);
+ computeAndAddLiveIns(LiveRegs, *StoreBB);
LoadCmpBB->clearLiveIns();
- computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
+ computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
return true;
}
@@ -915,7 +927,7 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
// .Lloadcmp:
// ldrexd rDestLo, rDestHi, [rAddr]
// cmp rDestLo, rDesiredLo
- // sbcs rTempReg<dead>, rDestHi, rDesiredHi
+ // sbcs dead rTempReg, rDestHi, rDesiredHi
// bne .Ldone
unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD;
MachineInstrBuilder MIB;
@@ -972,16 +984,15 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
MI.eraseFromParent();
// Recompute livein lists.
- const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
LivePhysRegs LiveRegs;
- computeLiveIns(LiveRegs, MRI, *DoneBB);
- computeLiveIns(LiveRegs, MRI, *StoreBB);
- computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
+ computeAndAddLiveIns(LiveRegs, *DoneBB);
+ computeAndAddLiveIns(LiveRegs, *StoreBB);
+ computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
// Do an extra pass around the loop to get loop carried registers right.
StoreBB->clearLiveIns();
- computeLiveIns(LiveRegs, MRI, *StoreBB);
+ computeAndAddLiveIns(LiveRegs, *StoreBB);
LoadCmpBB->clearLiveIns();
- computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
+ computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
return true;
}
@@ -1054,7 +1065,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
MI.getOperand(1).getReg())
.add(MI.getOperand(2))
.addImm(MI.getOperand(3).getImm()) // 'pred'
- .add(MI.getOperand(4));
+ .add(MI.getOperand(4))
+ .add(makeImplicit(MI.getOperand(1)));
MI.eraseFromParent();
return true;
@@ -1067,7 +1079,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
.add(MI.getOperand(2))
.addImm(MI.getOperand(3).getImm()) // 'pred'
.add(MI.getOperand(4))
- .add(condCodeOp()); // 's' bit
+ .add(condCodeOp()) // 's' bit
+ .add(makeImplicit(MI.getOperand(1)));
MI.eraseFromParent();
return true;
@@ -1079,7 +1092,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
.addImm(MI.getOperand(3).getImm())
.addImm(MI.getOperand(4).getImm()) // 'pred'
.add(MI.getOperand(5))
- .add(condCodeOp()); // 's' bit
+ .add(condCodeOp()) // 's' bit
+ .add(makeImplicit(MI.getOperand(1)));
MI.eraseFromParent();
return true;
@@ -1092,7 +1106,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
.addImm(MI.getOperand(4).getImm())
.addImm(MI.getOperand(5).getImm()) // 'pred'
.add(MI.getOperand(6))
- .add(condCodeOp()); // 's' bit
+ .add(condCodeOp()) // 's' bit
+ .add(makeImplicit(MI.getOperand(1)));
MI.eraseFromParent();
return true;
@@ -1104,7 +1119,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
MI.getOperand(1).getReg())
.addImm(MI.getOperand(2).getImm())
.addImm(MI.getOperand(3).getImm()) // 'pred'
- .add(MI.getOperand(4));
+ .add(MI.getOperand(4))
+ .add(makeImplicit(MI.getOperand(1)));
MI.eraseFromParent();
return true;
}
@@ -1116,7 +1132,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
.addImm(MI.getOperand(2).getImm())
.addImm(MI.getOperand(3).getImm()) // 'pred'
.add(MI.getOperand(4))
- .add(condCodeOp()); // 's' bit
+ .add(condCodeOp()) // 's' bit
+ .add(makeImplicit(MI.getOperand(1)));
MI.eraseFromParent();
return true;
@@ -1129,7 +1146,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
.addImm(MI.getOperand(2).getImm())
.addImm(MI.getOperand(3).getImm()) // 'pred'
.add(MI.getOperand(4))
- .add(condCodeOp()); // 's' bit
+ .add(condCodeOp()) // 's' bit
+ .add(makeImplicit(MI.getOperand(1)));
MI.eraseFromParent();
return true;
@@ -1152,7 +1170,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
.addImm(MI.getOperand(3).getImm())
.addImm(MI.getOperand(4).getImm()) // 'pred'
.add(MI.getOperand(5))
- .add(condCodeOp()); // 's' bit
+ .add(condCodeOp()) // 's' bit
+ .add(makeImplicit(MI.getOperand(1)));
MI.eraseFromParent();
return true;
}
@@ -1240,7 +1259,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
MachineConstantPool *MCP = MF->getConstantPool();
unsigned PCLabelID = AFI->createPICLabelUId();
MachineConstantPoolValue *CPV =
- ARMConstantPoolSymbol::Create(MF->getFunction()->getContext(),
+ ARMConstantPoolSymbol::Create(MF->getFunction().getContext(),
"__aeabi_read_tp", PCLabelID, 0);
unsigned Reg = MI.getOperand(0).getReg();
MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
@@ -1297,6 +1316,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
unsigned DstReg = MI.getOperand(0).getReg();
bool DstIsDead = MI.getOperand(0).isDead();
const MachineOperand &MO1 = MI.getOperand(1);
+ auto Flags = MO1.getTargetFlags();
const GlobalValue *GV = MO1.getGlobal();
bool IsARM =
Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs;
@@ -1315,9 +1335,13 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
if (IsPIC) {
unsigned PCAdj = IsARM ? 8 : 4;
+ auto Modifier = (Flags & ARMII::MO_GOT)
+ ? ARMCP::GOT_PREL
+ : ARMCP::no_modifier;
ARMPCLabelIndex = AFI->createPICLabelUId();
- CPV = ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex,
- ARMCP::CPValue, PCAdj);
+ CPV = ARMConstantPoolConstant::Create(
+ GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj, Modifier,
+ /*AddCurrentAddr*/ Modifier == ARMCP::GOT_PREL);
} else
CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier);
@@ -1445,7 +1469,9 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
// Copy the destination register.
- MIB.add(MI.getOperand(OpIdx++));
+ MachineOperand Dst(MI.getOperand(OpIdx++));
+ Dst.setIsRenamable(false);
+ MIB.add(Dst);
// Copy the predicate operands.
MIB.add(MI.getOperand(OpIdx++));
@@ -1698,9 +1724,8 @@ bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
AFI = MF.getInfo<ARMFunctionInfo>();
bool Modified = false;
- for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
- ++MFI)
- Modified |= ExpandMBB(*MFI);
+ for (MachineBasicBlock &MBB : MF)
+ Modified |= ExpandMBB(MBB);
if (VerifyARMPseudo)
MF.verify(this, "After expanding ARM pseudo instructions.");
return Modified;
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.