diff options
Diffstat (limited to 'gnu/llvm/lib/Target/ARM/ARMFastISel.cpp')
| -rw-r--r-- | gnu/llvm/lib/Target/ARM/ARMFastISel.cpp | 31 |
1 files changed, 16 insertions, 15 deletions
diff --git a/gnu/llvm/lib/Target/ARM/ARMFastISel.cpp b/gnu/llvm/lib/Target/ARM/ARMFastISel.cpp index 5dc93734ab5..60048d4453d 100644 --- a/gnu/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/gnu/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -1,4 +1,4 @@ -//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===// +//===- ARMFastISel.cpp - ARM FastISel implementation ----------------------===// // // The LLVM Compiler Infrastructure // @@ -23,17 +23,19 @@ #include "ARMSubtarget.h" #include "MCTargetDesc/ARMAddressingModes.h" #include "MCTargetDesc/ARMBaseInfo.h" +#include "Utils/ARMBaseInfo.h" #include "llvm/ADT/APFloat.h" #include "llvm/ADT/APInt.h" #include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/FastISel.h" #include "llvm/CodeGen/FunctionLoweringInfo.h" #include "llvm/CodeGen/ISDOpcodes.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineMemOperand.h" @@ -41,6 +43,10 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineValueType.h" #include "llvm/CodeGen/RuntimeLibcalls.h" +#include "llvm/CodeGen/TargetInstrInfo.h" +#include "llvm/CodeGen/TargetLowering.h" +#include "llvm/CodeGen/TargetOpcodes.h" +#include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/IR/Argument.h" #include "llvm/IR/Attributes.h" @@ -58,6 +64,7 @@ #include "llvm/IR/Instruction.h" #include "llvm/IR/Instructions.h" #include "llvm/IR/IntrinsicInst.h" +#include "llvm/IR/Intrinsics.h" #include "llvm/IR/Module.h" #include "llvm/IR/Operator.h" #include "llvm/IR/Type.h" @@ -69,8 +76,6 @@ #include "llvm/Support/Compiler.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" -#include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include <cassert> @@ -82,7 +87,7 @@ using namespace llvm; namespace { // All possible address modes, plus some. - typedef struct Address { + struct Address { enum { RegBase, FrameIndexBase @@ -99,7 +104,7 @@ namespace { Address() { Base.Reg = 0; } - } Address; + }; class ARMFastISel final : public FastISel { /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can @@ -1411,7 +1416,7 @@ bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value, case MVT::i8: case MVT::i16: needsExt = true; - // Intentional fall-through. + LLVM_FALLTHROUGH; case MVT::i32: if (isThumb2) { if (!UseImm) @@ -1848,7 +1853,7 @@ CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) { switch (CC) { default: - llvm_unreachable("Unsupported calling convention"); + report_fatal_error("Unsupported calling convention"); case CallingConv::Fast: if (Subtarget->hasVFP2() && !isVarArg) { if (!Subtarget->isAAPCS_ABI()) @@ -1882,7 +1887,7 @@ CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); case CallingConv::GHC: if (Return) - llvm_unreachable("Can't return in GHC call convention"); + report_fatal_error("Can't return in GHC call convention"); else return CC_ARM_APCS_GHC; } @@ -2890,13 +2895,11 @@ bool ARMFastISel::fastSelectInstruction(const Instruction *I) { return false; } -namespace { - // This table describes sign- and zero-extend instructions which can be // folded into a preceding load. All of these extends have an immediate // (sometimes a mask and sometimes a shift) that's applied after // extension. -const struct FoldableLoadExtendsStruct { +static const struct FoldableLoadExtendsStruct { uint16_t Opc[2]; // ARM, Thumb. uint8_t ExpectedImm; uint8_t isZExt : 1; @@ -2909,8 +2912,6 @@ const struct FoldableLoadExtendsStruct { { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 } }; -} // end anonymous namespace - /// \brief The specified machine instr operand is a vreg, and that /// vreg is being provided by the specified load instruction. If possible, /// try to fold the load as an operand to the instruction, returning true if @@ -2957,7 +2958,7 @@ unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT) { bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV); - LLVMContext *Context = &MF->getFunction()->getContext(); + LLVMContext *Context = &MF->getFunction().getContext(); unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create( |