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-rw-r--r--gnu/llvm/lib/Target/Mips/Mips.td5
1 files changed, 5 insertions, 0 deletions
diff --git a/gnu/llvm/lib/Target/Mips/Mips.td b/gnu/llvm/lib/Target/Mips/Mips.td
index 35352b6115c..ea3fa0a9578 100644
--- a/gnu/llvm/lib/Target/Mips/Mips.td
+++ b/gnu/llvm/lib/Target/Mips/Mips.td
@@ -24,6 +24,8 @@ class PredicateControl {
list<Predicate> EncodingPredicates = [];
// Predicates for the GPR size such as IsGP64bit
list<Predicate> GPRPredicates = [];
+ // Predicates for the PTR size such as IsPTR64bit
+ list<Predicate> PTRPredicates = [];
// Predicates for the FGR size and layout such as IsFP64bit
list<Predicate> FGRPredicates = [];
// Predicates for the instruction group membership such as ISA's and ASE's
@@ -34,6 +36,7 @@ class PredicateControl {
list<Predicate> AdditionalPredicates = [];
list<Predicate> Predicates = !listconcat(EncodingPredicates,
GPRPredicates,
+ PTRPredicates,
FGRPredicates,
InsnPredicates,
HardFloatPredicate,
@@ -62,6 +65,8 @@ def MipsInstrInfo : InstrInfo;
def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true",
"Disable SVR4-style position-independent code">;
+def FeaturePTR64Bit : SubtargetFeature<"ptr64", "IsPTR64bit", "true",
+ "Pointers are 64-bit wide">;
def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
"General Purpose Registers are 64-bit wide">;
def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",