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-rw-r--r--gnu/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp23
1 files changed, 11 insertions, 12 deletions
diff --git a/gnu/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/gnu/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
index 735461c2a79..eb1eea7925c 100644
--- a/gnu/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
+++ b/gnu/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
@@ -1,4 +1,4 @@
-//===-- MipsSEFrameLowering.cpp - Mips32/64 Frame Information -------------===//
+//===- MipsSEFrameLowering.cpp - Mips32/64 Frame Information --------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -29,6 +29,9 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCDwarf.h"
@@ -37,9 +40,6 @@
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <utility>
@@ -71,7 +71,7 @@ public:
bool expand();
private:
- typedef MachineBasicBlock::iterator Iter;
+ using Iter = MachineBasicBlock::iterator;
bool expandInstr(MachineBasicBlock &MBB, Iter I);
void expandLoadCCond(MachineBasicBlock &MBB, Iter I);
@@ -390,7 +390,7 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
}
MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI)
- : MipsFrameLowering(STI, STI.stackAlignment()) {}
+ : MipsFrameLowering(STI, STI.getStackAlignment()) {}
void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
@@ -424,7 +424,6 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
MachineModuleInfo &MMI = MF.getMMI();
const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
- MachineLocation DstML, SrcML;
// Adjust stack.
TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
@@ -435,7 +434,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
- if (MF.getFunction()->hasFnAttribute("interrupt"))
+ if (MF.getFunction().hasFnAttribute("interrupt"))
emitInterruptPrologueStub(MF, MBB);
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
@@ -583,7 +582,7 @@ void MipsSEFrameLowering::emitInterruptPrologueStub(
// Perform ISR handling like GCC
StringRef IntKind =
- MF.getFunction()->getFnAttribute("interrupt").getValueAsString();
+ MF.getFunction().getFnAttribute("interrupt").getValueAsString();
const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;
// EIC interrupt handling needs to read the Cause register to disable
@@ -727,7 +726,7 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
}
}
- if (MF.getFunction()->hasFnAttribute("interrupt"))
+ if (MF.getFunction().hasFnAttribute("interrupt"))
emitInterruptEpilogueStub(MF, MBB);
// Get the number of bytes from FrameInfo
@@ -810,8 +809,8 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
// spilled to the stack frame.
bool IsLOHI = (Reg == Mips::LO0 || Reg == Mips::LO0_64 ||
Reg == Mips::HI0 || Reg == Mips::HI0_64);
- const Function *Func = MBB.getParent()->getFunction();
- if (IsLOHI && Func->hasFnAttribute("interrupt")) {
+ const Function &Func = MBB.getParent()->getFunction();
+ if (IsLOHI && Func.hasFnAttribute("interrupt")) {
DebugLoc DL = MI->getDebugLoc();
unsigned Op = 0;