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-rw-r--r--lib/libunwind/src/Registers.hpp214
-rw-r--r--lib/libunwind/src/UnwindRegistersRestore.S91
-rw-r--r--lib/libunwind/src/UnwindRegistersSave.S91
-rw-r--r--lib/libunwind/src/libunwind.cpp4
4 files changed, 385 insertions, 15 deletions
diff --git a/lib/libunwind/src/Registers.hpp b/lib/libunwind/src/Registers.hpp
index 888d07be5b2..9aadaf4caf5 100644
--- a/lib/libunwind/src/Registers.hpp
+++ b/lib/libunwind/src/Registers.hpp
@@ -2793,6 +2793,7 @@ public:
void setSP(uint32_t value) { _registers.__r[29] = value; }
uint32_t getIP() const { return _registers.__pc; }
void setIP(uint32_t value) { _registers.__pc = value; }
+ uint32_t getWCookie() const { return 0; }
private:
struct mips_o32_thread_state_t {
@@ -2803,6 +2804,14 @@ private:
};
mips_o32_thread_state_t _registers;
+#ifdef __mips_hard_float
+ /// O32 with 32-bit floating point registers only uses half of this
+ /// space. However, using the same layout for 32-bit vs 64-bit
+ /// floating point registers results in a single context size for
+ /// O32 with hard float.
+ uint32_t _padding;
+ double _floats[32];
+#endif
};
inline Registers_mips_o32::Registers_mips_o32(const void *registers) {
@@ -2829,13 +2838,28 @@ inline bool Registers_mips_o32::validRegister(int regNum) const {
return true;
if (regNum == UNW_MIPS_LO)
return true;
- // FIXME: Hard float, DSP accumulator registers, MSA registers
+#if defined(__mips_hard_float) && __mips_fpr == 32
+ if (regNum >= UNW_MIPS_F0 && regNum <= UNW_MIPS_F31)
+ return true;
+#endif
+ // FIXME: DSP accumulator registers, MSA registers
return false;
}
inline uint32_t Registers_mips_o32::getRegister(int regNum) const {
if (regNum >= UNW_MIPS_R0 && regNum <= UNW_MIPS_R31)
return _registers.__r[regNum - UNW_MIPS_R0];
+#if defined(__mips_hard_float) && __mips_fpr == 32
+ if (regNum >= UNW_MIPS_F0 && regNum <= UNW_MIPS_F31) {
+ uint32_t *p;
+
+ if (regNum % 2 == 0)
+ p = (uint32_t *)&_floats[regNum - UNW_MIPS_F0];
+ else
+ p = (uint32_t *)&_floats[(regNum - 1) - UNW_MIPS_F0] + 1;
+ return *p;
+ }
+#endif
switch (regNum) {
case UNW_REG_IP:
@@ -2855,6 +2879,18 @@ inline void Registers_mips_o32::setRegister(int regNum, uint32_t value) {
_registers.__r[regNum - UNW_MIPS_R0] = value;
return;
}
+#if defined(__mips_hard_float) && __mips_fpr == 32
+ if (regNum >= UNW_MIPS_F0 && regNum <= UNW_MIPS_F31) {
+ uint32_t *p;
+
+ if (regNum % 2 == 0)
+ p = (uint32_t *)&_floats[regNum - UNW_MIPS_F0];
+ else
+ p = (uint32_t *)&_floats[(regNum - 1) - UNW_MIPS_F0] + 1;
+ *p = value;
+ return;
+ }
+#endif
switch (regNum) {
case UNW_REG_IP:
@@ -2873,17 +2909,31 @@ inline void Registers_mips_o32::setRegister(int regNum, uint32_t value) {
_LIBUNWIND_ABORT("unsupported mips_o32 register");
}
-inline bool Registers_mips_o32::validFloatRegister(int /* regNum */) const {
+inline bool Registers_mips_o32::validFloatRegister(int regNum) const {
+#if defined(__mips_hard_float) && __mips_fpr == 64
+ if (regNum >= UNW_MIPS_F0 && regNum <= UNW_MIPS_F31)
+ return true;
+#endif
return false;
}
-inline double Registers_mips_o32::getFloatRegister(int /* regNum */) const {
+inline double Registers_mips_o32::getFloatRegister(int regNum) const {
+#if defined(__mips_hard_float) && __mips_fpr == 64
+ assert(validFloatRegister(regNum));
+ return _floats[regNum - UNW_MIPS_F0];
+#else
_LIBUNWIND_ABORT("mips_o32 float support not implemented");
+#endif
}
-inline void Registers_mips_o32::setFloatRegister(int /* regNum */,
- double /* value */) {
+inline void Registers_mips_o32::setFloatRegister(int regNum,
+ double value) {
+#if defined(__mips_hard_float) && __mips_fpr == 64
+ assert(validFloatRegister(regNum));
+ _floats[regNum - UNW_MIPS_F0] = value;
+#else
_LIBUNWIND_ABORT("mips_o32 float support not implemented");
+#endif
}
inline bool Registers_mips_o32::validVectorRegister(int /* regNum */) const {
@@ -2964,6 +3014,70 @@ inline const char *Registers_mips_o32::getRegisterName(int regNum) {
return "$30";
case UNW_MIPS_R31:
return "$31";
+ case UNW_MIPS_F0:
+ return "$f0";
+ case UNW_MIPS_F1:
+ return "$f1";
+ case UNW_MIPS_F2:
+ return "$f2";
+ case UNW_MIPS_F3:
+ return "$f3";
+ case UNW_MIPS_F4:
+ return "$f4";
+ case UNW_MIPS_F5:
+ return "$f5";
+ case UNW_MIPS_F6:
+ return "$f6";
+ case UNW_MIPS_F7:
+ return "$f7";
+ case UNW_MIPS_F8:
+ return "$f8";
+ case UNW_MIPS_F9:
+ return "$f9";
+ case UNW_MIPS_F10:
+ return "$f10";
+ case UNW_MIPS_F11:
+ return "$f11";
+ case UNW_MIPS_F12:
+ return "$f12";
+ case UNW_MIPS_F13:
+ return "$f13";
+ case UNW_MIPS_F14:
+ return "$f14";
+ case UNW_MIPS_F15:
+ return "$f15";
+ case UNW_MIPS_F16:
+ return "$f16";
+ case UNW_MIPS_F17:
+ return "$f17";
+ case UNW_MIPS_F18:
+ return "$f18";
+ case UNW_MIPS_F19:
+ return "$f19";
+ case UNW_MIPS_F20:
+ return "$f20";
+ case UNW_MIPS_F21:
+ return "$f21";
+ case UNW_MIPS_F22:
+ return "$f22";
+ case UNW_MIPS_F23:
+ return "$f23";
+ case UNW_MIPS_F24:
+ return "$f24";
+ case UNW_MIPS_F25:
+ return "$f25";
+ case UNW_MIPS_F26:
+ return "$f26";
+ case UNW_MIPS_F27:
+ return "$f27";
+ case UNW_MIPS_F28:
+ return "$f28";
+ case UNW_MIPS_F29:
+ return "$f29";
+ case UNW_MIPS_F30:
+ return "$f30";
+ case UNW_MIPS_F31:
+ return "$f31";
case UNW_MIPS_HI:
return "$hi";
case UNW_MIPS_LO:
@@ -2999,6 +3113,7 @@ public:
void setSP(uint64_t value) { _registers.__r[29] = value; }
uint64_t getIP() const { return _registers.__pc; }
void setIP(uint64_t value) { _registers.__pc = value; }
+ uint32_t getWCookie() const { return 0; }
private:
struct mips_n64_thread_state_t {
@@ -3009,6 +3124,9 @@ private:
};
mips_n64_thread_state_t _registers;
+#ifdef __mips_hard_float
+ double _floats[32];
+#endif
};
inline Registers_mips_n64::Registers_mips_n64(const void *registers) {
@@ -3079,17 +3197,31 @@ inline void Registers_mips_n64::setRegister(int regNum, uint64_t value) {
_LIBUNWIND_ABORT("unsupported mips_n64 register");
}
-inline bool Registers_mips_n64::validFloatRegister(int /* regNum */) const {
+inline bool Registers_mips_n64::validFloatRegister(int regNum) const {
+#ifdef __mips_hard_float
+ if (regNum >= UNW_MIPS_F0 && regNum <= UNW_MIPS_F31)
+ return true;
+#endif
return false;
}
-inline double Registers_mips_n64::getFloatRegister(int /* regNum */) const {
+inline double Registers_mips_n64::getFloatRegister(int regNum) const {
+#ifdef __mips_hard_float
+ assert(validFloatRegister(regNum));
+ return _floats[regNum - UNW_MIPS_F0];
+#else
_LIBUNWIND_ABORT("mips_n64 float support not implemented");
+#endif
}
-inline void Registers_mips_n64::setFloatRegister(int /* regNum */,
- double /* value */) {
+inline void Registers_mips_n64::setFloatRegister(int regNum,
+ double value) {
+#ifdef __mips_hard_float
+ assert(validFloatRegister(regNum));
+ _floats[regNum - UNW_MIPS_F0] = value;
+#else
_LIBUNWIND_ABORT("mips_n64 float support not implemented");
+#endif
}
inline bool Registers_mips_n64::validVectorRegister(int /* regNum */) const {
@@ -3170,6 +3302,70 @@ inline const char *Registers_mips_n64::getRegisterName(int regNum) {
return "$30";
case UNW_MIPS_R31:
return "$31";
+ case UNW_MIPS_F0:
+ return "$f0";
+ case UNW_MIPS_F1:
+ return "$f1";
+ case UNW_MIPS_F2:
+ return "$f2";
+ case UNW_MIPS_F3:
+ return "$f3";
+ case UNW_MIPS_F4:
+ return "$f4";
+ case UNW_MIPS_F5:
+ return "$f5";
+ case UNW_MIPS_F6:
+ return "$f6";
+ case UNW_MIPS_F7:
+ return "$f7";
+ case UNW_MIPS_F8:
+ return "$f8";
+ case UNW_MIPS_F9:
+ return "$f9";
+ case UNW_MIPS_F10:
+ return "$f10";
+ case UNW_MIPS_F11:
+ return "$f11";
+ case UNW_MIPS_F12:
+ return "$f12";
+ case UNW_MIPS_F13:
+ return "$f13";
+ case UNW_MIPS_F14:
+ return "$f14";
+ case UNW_MIPS_F15:
+ return "$f15";
+ case UNW_MIPS_F16:
+ return "$f16";
+ case UNW_MIPS_F17:
+ return "$f17";
+ case UNW_MIPS_F18:
+ return "$f18";
+ case UNW_MIPS_F19:
+ return "$f19";
+ case UNW_MIPS_F20:
+ return "$f20";
+ case UNW_MIPS_F21:
+ return "$f21";
+ case UNW_MIPS_F22:
+ return "$f22";
+ case UNW_MIPS_F23:
+ return "$f23";
+ case UNW_MIPS_F24:
+ return "$f24";
+ case UNW_MIPS_F25:
+ return "$f25";
+ case UNW_MIPS_F26:
+ return "$f26";
+ case UNW_MIPS_F27:
+ return "$f27";
+ case UNW_MIPS_F28:
+ return "$f28";
+ case UNW_MIPS_F29:
+ return "$f29";
+ case UNW_MIPS_F30:
+ return "$f30";
+ case UNW_MIPS_F31:
+ return "$f31";
case UNW_MIPS_HI:
return "$hi";
case UNW_MIPS_LO:
diff --git a/lib/libunwind/src/UnwindRegistersRestore.S b/lib/libunwind/src/UnwindRegistersRestore.S
index 94141de2eb5..0e1336d8f4c 100644
--- a/lib/libunwind/src/UnwindRegistersRestore.S
+++ b/lib/libunwind/src/UnwindRegistersRestore.S
@@ -672,7 +672,7 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind17Registers_sparc646jumptoEv)
jmpl %o7, %g0
ldx [%o0 + 0x40], %o0
-#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float)
+#elif defined(__mips__) && defined(_ABIO32)
//
// void libunwind::Registers_mips_o32::jumpto()
@@ -685,6 +685,59 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv)
.set noat
.set noreorder
.set nomacro
+#ifdef __mips_hard_float
+#if __mips_fpr == 32
+ ldc1 $f0, (4 * 36 + 8 * 0)($4)
+ ldc1 $f2, (4 * 36 + 8 * 2)($4)
+ ldc1 $f4, (4 * 36 + 8 * 4)($4)
+ ldc1 $f6, (4 * 36 + 8 * 6)($4)
+ ldc1 $f8, (4 * 36 + 8 * 8)($4)
+ ldc1 $f10, (4 * 36 + 8 * 10)($4)
+ ldc1 $f12, (4 * 36 + 8 * 12)($4)
+ ldc1 $f14, (4 * 36 + 8 * 14)($4)
+ ldc1 $f16, (4 * 36 + 8 * 16)($4)
+ ldc1 $f18, (4 * 36 + 8 * 18)($4)
+ ldc1 $f20, (4 * 36 + 8 * 20)($4)
+ ldc1 $f22, (4 * 36 + 8 * 22)($4)
+ ldc1 $f24, (4 * 36 + 8 * 24)($4)
+ ldc1 $f26, (4 * 36 + 8 * 26)($4)
+ ldc1 $f28, (4 * 36 + 8 * 28)($4)
+ ldc1 $f30, (4 * 36 + 8 * 30)($4)
+#else
+ ldc1 $f0, (4 * 36 + 8 * 0)($4)
+ ldc1 $f1, (4 * 36 + 8 * 1)($4)
+ ldc1 $f2, (4 * 36 + 8 * 2)($4)
+ ldc1 $f3, (4 * 36 + 8 * 3)($4)
+ ldc1 $f4, (4 * 36 + 8 * 4)($4)
+ ldc1 $f5, (4 * 36 + 8 * 5)($4)
+ ldc1 $f6, (4 * 36 + 8 * 6)($4)
+ ldc1 $f7, (4 * 36 + 8 * 7)($4)
+ ldc1 $f8, (4 * 36 + 8 * 8)($4)
+ ldc1 $f9, (4 * 36 + 8 * 9)($4)
+ ldc1 $f10, (4 * 36 + 8 * 10)($4)
+ ldc1 $f11, (4 * 36 + 8 * 11)($4)
+ ldc1 $f12, (4 * 36 + 8 * 12)($4)
+ ldc1 $f13, (4 * 36 + 8 * 13)($4)
+ ldc1 $f14, (4 * 36 + 8 * 14)($4)
+ ldc1 $f15, (4 * 36 + 8 * 15)($4)
+ ldc1 $f16, (4 * 36 + 8 * 16)($4)
+ ldc1 $f17, (4 * 36 + 8 * 17)($4)
+ ldc1 $f18, (4 * 36 + 8 * 18)($4)
+ ldc1 $f19, (4 * 36 + 8 * 19)($4)
+ ldc1 $f20, (4 * 36 + 8 * 20)($4)
+ ldc1 $f21, (4 * 36 + 8 * 21)($4)
+ ldc1 $f22, (4 * 36 + 8 * 22)($4)
+ ldc1 $f23, (4 * 36 + 8 * 23)($4)
+ ldc1 $f24, (4 * 36 + 8 * 24)($4)
+ ldc1 $f25, (4 * 36 + 8 * 25)($4)
+ ldc1 $f26, (4 * 36 + 8 * 26)($4)
+ ldc1 $f27, (4 * 36 + 8 * 27)($4)
+ ldc1 $f28, (4 * 36 + 8 * 28)($4)
+ ldc1 $f29, (4 * 36 + 8 * 29)($4)
+ ldc1 $f30, (4 * 36 + 8 * 30)($4)
+ ldc1 $f31, (4 * 36 + 8 * 31)($4)
+#endif
+#endif
// restore hi and lo
lw $8, (4 * 33)($4)
mthi $8
@@ -728,7 +781,7 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv)
lw $4, (4 * 4)($4)
.set pop
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips__) && defined(_ABI64)
//
// void libunwind::Registers_mips_n64::jumpto()
@@ -741,6 +794,40 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_n646jumptoEv)
.set noat
.set noreorder
.set nomacro
+#ifdef __mips_hard_float
+ ldc1 $f0, (8 * 35)($4)
+ ldc1 $f1, (8 * 36)($4)
+ ldc1 $f2, (8 * 37)($4)
+ ldc1 $f3, (8 * 38)($4)
+ ldc1 $f4, (8 * 39)($4)
+ ldc1 $f5, (8 * 40)($4)
+ ldc1 $f6, (8 * 41)($4)
+ ldc1 $f7, (8 * 42)($4)
+ ldc1 $f8, (8 * 43)($4)
+ ldc1 $f9, (8 * 44)($4)
+ ldc1 $f10, (8 * 45)($4)
+ ldc1 $f11, (8 * 46)($4)
+ ldc1 $f12, (8 * 47)($4)
+ ldc1 $f13, (8 * 48)($4)
+ ldc1 $f14, (8 * 49)($4)
+ ldc1 $f15, (8 * 50)($4)
+ ldc1 $f16, (8 * 51)($4)
+ ldc1 $f17, (8 * 52)($4)
+ ldc1 $f18, (8 * 53)($4)
+ ldc1 $f19, (8 * 54)($4)
+ ldc1 $f20, (8 * 55)($4)
+ ldc1 $f21, (8 * 56)($4)
+ ldc1 $f22, (8 * 57)($4)
+ ldc1 $f23, (8 * 58)($4)
+ ldc1 $f24, (8 * 59)($4)
+ ldc1 $f25, (8 * 60)($4)
+ ldc1 $f26, (8 * 61)($4)
+ ldc1 $f27, (8 * 62)($4)
+ ldc1 $f28, (8 * 63)($4)
+ ldc1 $f29, (8 * 64)($4)
+ ldc1 $f30, (8 * 65)($4)
+ ldc1 $f31, (8 * 66)($4)
+#endif
// restore hi and lo
ld $8, (8 * 33)($4)
mthi $8
diff --git a/lib/libunwind/src/UnwindRegistersSave.S b/lib/libunwind/src/UnwindRegistersSave.S
index 81d413c4874..bf951d642c1 100644
--- a/lib/libunwind/src/UnwindRegistersSave.S
+++ b/lib/libunwind/src/UnwindRegistersSave.S
@@ -116,7 +116,7 @@ DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
xorl %eax, %eax # return UNW_ESUCCESS
ret
-#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float)
+#elif defined(__mips__) && defined(_ABIO32)
#
# extern int unw_getcontext(unw_context_t* thread_state)
@@ -167,12 +167,65 @@ DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
sw $8, (4 * 33)($4)
mflo $8
sw $8, (4 * 34)($4)
+#ifdef __mips_hard_float
+#if __mips_fpr == 32
+ sdc1 $f0, (4 * 36 + 8 * 0)($4)
+ sdc1 $f2, (4 * 36 + 8 * 2)($4)
+ sdc1 $f4, (4 * 36 + 8 * 4)($4)
+ sdc1 $f6, (4 * 36 + 8 * 6)($4)
+ sdc1 $f8, (4 * 36 + 8 * 8)($4)
+ sdc1 $f10, (4 * 36 + 8 * 10)($4)
+ sdc1 $f12, (4 * 36 + 8 * 12)($4)
+ sdc1 $f14, (4 * 36 + 8 * 14)($4)
+ sdc1 $f16, (4 * 36 + 8 * 16)($4)
+ sdc1 $f18, (4 * 36 + 8 * 18)($4)
+ sdc1 $f20, (4 * 36 + 8 * 20)($4)
+ sdc1 $f22, (4 * 36 + 8 * 22)($4)
+ sdc1 $f24, (4 * 36 + 8 * 24)($4)
+ sdc1 $f26, (4 * 36 + 8 * 26)($4)
+ sdc1 $f28, (4 * 36 + 8 * 28)($4)
+ sdc1 $f30, (4 * 36 + 8 * 30)($4)
+#else
+ sdc1 $f0, (4 * 36 + 8 * 0)($4)
+ sdc1 $f1, (4 * 36 + 8 * 1)($4)
+ sdc1 $f2, (4 * 36 + 8 * 2)($4)
+ sdc1 $f3, (4 * 36 + 8 * 3)($4)
+ sdc1 $f4, (4 * 36 + 8 * 4)($4)
+ sdc1 $f5, (4 * 36 + 8 * 5)($4)
+ sdc1 $f6, (4 * 36 + 8 * 6)($4)
+ sdc1 $f7, (4 * 36 + 8 * 7)($4)
+ sdc1 $f8, (4 * 36 + 8 * 8)($4)
+ sdc1 $f9, (4 * 36 + 8 * 9)($4)
+ sdc1 $f10, (4 * 36 + 8 * 10)($4)
+ sdc1 $f11, (4 * 36 + 8 * 11)($4)
+ sdc1 $f12, (4 * 36 + 8 * 12)($4)
+ sdc1 $f13, (4 * 36 + 8 * 13)($4)
+ sdc1 $f14, (4 * 36 + 8 * 14)($4)
+ sdc1 $f15, (4 * 36 + 8 * 15)($4)
+ sdc1 $f16, (4 * 36 + 8 * 16)($4)
+ sdc1 $f17, (4 * 36 + 8 * 17)($4)
+ sdc1 $f18, (4 * 36 + 8 * 18)($4)
+ sdc1 $f19, (4 * 36 + 8 * 19)($4)
+ sdc1 $f20, (4 * 36 + 8 * 20)($4)
+ sdc1 $f21, (4 * 36 + 8 * 21)($4)
+ sdc1 $f22, (4 * 36 + 8 * 22)($4)
+ sdc1 $f23, (4 * 36 + 8 * 23)($4)
+ sdc1 $f24, (4 * 36 + 8 * 24)($4)
+ sdc1 $f25, (4 * 36 + 8 * 25)($4)
+ sdc1 $f26, (4 * 36 + 8 * 26)($4)
+ sdc1 $f27, (4 * 36 + 8 * 27)($4)
+ sdc1 $f28, (4 * 36 + 8 * 28)($4)
+ sdc1 $f29, (4 * 36 + 8 * 29)($4)
+ sdc1 $f30, (4 * 36 + 8 * 30)($4)
+ sdc1 $f31, (4 * 36 + 8 * 31)($4)
+#endif
+#endif
jr $31
# return UNW_ESUCCESS
or $2, $0, $0
.set pop
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips__) && defined(_ABI64)
#
# extern int unw_getcontext(unw_context_t* thread_state)
@@ -223,6 +276,40 @@ DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
sd $8, (8 * 33)($4)
mflo $8
sd $8, (8 * 34)($4)
+#ifdef __mips_hard_float
+ sdc1 $f0, (8 * 35)($4)
+ sdc1 $f1, (8 * 36)($4)
+ sdc1 $f2, (8 * 37)($4)
+ sdc1 $f3, (8 * 38)($4)
+ sdc1 $f4, (8 * 39)($4)
+ sdc1 $f5, (8 * 40)($4)
+ sdc1 $f6, (8 * 41)($4)
+ sdc1 $f7, (8 * 42)($4)
+ sdc1 $f8, (8 * 43)($4)
+ sdc1 $f9, (8 * 44)($4)
+ sdc1 $f10, (8 * 45)($4)
+ sdc1 $f11, (8 * 46)($4)
+ sdc1 $f12, (8 * 47)($4)
+ sdc1 $f13, (8 * 48)($4)
+ sdc1 $f14, (8 * 49)($4)
+ sdc1 $f15, (8 * 50)($4)
+ sdc1 $f16, (8 * 51)($4)
+ sdc1 $f17, (8 * 52)($4)
+ sdc1 $f18, (8 * 53)($4)
+ sdc1 $f19, (8 * 54)($4)
+ sdc1 $f20, (8 * 55)($4)
+ sdc1 $f21, (8 * 56)($4)
+ sdc1 $f22, (8 * 57)($4)
+ sdc1 $f23, (8 * 58)($4)
+ sdc1 $f24, (8 * 59)($4)
+ sdc1 $f25, (8 * 60)($4)
+ sdc1 $f26, (8 * 61)($4)
+ sdc1 $f27, (8 * 62)($4)
+ sdc1 $f28, (8 * 63)($4)
+ sdc1 $f29, (8 * 64)($4)
+ sdc1 $f30, (8 * 65)($4)
+ sdc1 $f31, (8 * 66)($4)
+#endif
jr $31
# return UNW_ESUCCESS
or $2, $0, $0
diff --git a/lib/libunwind/src/libunwind.cpp b/lib/libunwind/src/libunwind.cpp
index d94c8cfb955..632535ac470 100644
--- a/lib/libunwind/src/libunwind.cpp
+++ b/lib/libunwind/src/libunwind.cpp
@@ -61,9 +61,9 @@ _LIBUNWIND_EXPORT int unw_init_local(unw_cursor_t *cursor,
# define REGISTER_KIND Registers_arm
#elif defined(__or1k__)
# define REGISTER_KIND Registers_or1k
-#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float)
+#elif defined(__mips__) && defined(_ABIO32)
# define REGISTER_KIND Registers_mips_o32
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips__) && defined(_ABI64)
# define REGISTER_KIND Registers_mips_n64
#elif defined(__mips__)
# warning The MIPS architecture is not supported with this ABI and environment!
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