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* Mitigate Intel's Microarchitectural Data Sampling vulnerability.guenther2019-05-171-1/+4
| | | | | | | | | | | | | | | | If the CPU has the new VERW behavior than that is used, otherwise use the proper sequence from Intel's "Deep Dive" doc is used in the return-to-userspace and enter-VMM-guest paths. The enter-C3-idle path is not mitigated because it's only a problem when SMT/HT is enabled: mitigating everything when that's enabled would be a _huge_ set of changes that we see no point in doing. Update vmm(4) to pass through the MSR bits so that guests can apply the optimal mitigation. VMM help and specific feedback from mlarkin@ vendor-portability help from jsg@ and kettenis@ ok kettenis@ mlarkin@ deraadt@ jsg@
* vmm: add host side pvclockpd2019-05-131-1/+5
| | | | | | | | | Emulate kvm pvclock in vmm(4). Compatible with pvclock(4) in OpenBSD. Linux does not attach to this (yet). Fixes by reyk@ and tested extensively by reyk@, tb@ and phessler@ ok mlarkin@ phessler@ reyk@
* vmm: add a x86 page table walkerpd2019-05-121-1/+2
| | | | | | | | | | Add a first cut of x86 page table walker to vmd(8) and vmm(4). This function is not used right now but is a building block for future features like HPET, OUTSB and INSB emulation, nested virtualisation support, etc. With help from Mike Larkin ok mlarkin@
* vmm(4): Don't advertise support for SSBD and related speculative execmlarkin2019-04-011-1/+6
| | | | | | | | | | | control features on AMD. Linux tries to use them and since these are not fully implemented yet, it results in an OOPS during boot on recent hardware. When these are properly passed through, we can restore advertising support for this feature. ok deraadt@
* vmm(4): Don't advertise support for MCE/MCA since we don't implementmlarkin2019-04-011-2/+3
| | | | | | | the MSRs to support them. Fixes an OOPS during Linux guest VM boot on Ryzen. ok deraadt
* Bump VMM_MAX_NAME_LEN to 64 to allow for longer vm names.ajacoutot2019-03-021-2/+2
| | | | ok mlarkin@
* vmm(4): allow preservation and restoration of guest debug registersmlarkin2019-02-201-2/+22
| | | | | | Allow save/restore of %drX registers during VM exit and entry discussed with deraadt@
* vmm(4): Clear the guest MWAITX/MONITORX extended CPUID feature bit,brynet2018-09-201-3/+4
| | | | | | | | | like we already do for MWAIT/MONITOR. Also match Intel here by not exposing the SVM capability to AMD guests. Allows Linux guests to boot in vmd(8) on Ryzen CPUs. ok mlarkin@
* Perform mitigations for Intel L1TF screwup. There are three options:deraadt2018-08-211-2/+2
| | | | | | | | | | | | | | | (1) Future cpus which don't have the bug, (2) cpu's with microcode containing a L1D flush operation, (3) stuffing the L1D cache with fresh data and expiring old content. This stuffing loop is complicated and interesting, no details on the mitigation have been released by Intel so Mike and I studied other systems for inspiration. Replacement algorithm for the L1D is described in the tlbleed paper. We use a 64K PA-linear region filled with trapsleds (in case there is L1D->L1I data movement). The TLBs covering the region are loaded first, because TLB loading apparently flows through the D cache. Before performing vmlaunch or vmresume, the cachelines covering the guest registers are also flushed. with mlarkin, additional testing by pd, handy comments from the kettenis and guenther peanuts
* zap an extra newlinemlarkin2018-07-121-2/+1
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* vmm(8)/vmm(4): send a copy of the guest register state to vmd on exit,mlarkin2018-07-121-13/+18
| | | | | | | avoiding multiple readregs ioctls back to vmm in case register content is needed subsequently. ok phessler
* vmm(4): return proper cache topology for cpuid(0x4)mlarkin2018-07-111-1/+6
| | | | | | | Make the cache neighbor fields match the number of VCPUs present (currently 1) ok reyk
* forgot to commit vmmvar.h needed by previous two commits, thanks ccardenasmlarkin2018-07-051-1/+10
| | | | for noticing.
* vmm(4): pass through ELCRx ports to vmd(8)mlarkin2018-04-271-2/+4
| | | | | These ports are used for Edge/Level control on the legacy PIC and will be needed for a subsequent commit.
* vmm(4): passthrough port 0x61 to vmd(8)mlarkin2018-04-261-1/+6
| | | | ok guenther
* Remove RDTSCP from the CPUID flags reported to the guest VM. The instructionmlarkin2018-03-291-1/+7
| | | | | | | was already disabled, but reporting it as available and then failing it caused SmartOS to crash during boot. ok pd@
* make vmm(4) less responsible for initial register state, preferring to letmlarkin2017-11-291-2/+6
| | | | | | usermode daemons handle that. ok pd@
* add some comments. no functional changemlarkin2017-11-291-6/+18
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* vmmvar.h changes for upcoming cdrom support in vmd(8).mlarkin2017-11-171-1/+3
| | | | Diff from carlos cardenas, thanks
* vmd: Allow only upward migrationpd2017-08-201-1/+65
| | | | | | | | | | This restricts receiving vms from hosts with more cpu features. Tested on broadwell -> skylake (works) skylake -> broadwell (don't work) ok mlarkin@
* vmm: add #defines for exception vectors that can be used to injectmlarkin2017-08-141-1/+26
| | | | various events into the guest
* vmm: handle IA32_MISC_ENABLE MSR. Bits set in this MSR can result inmlarkin2017-08-121-3/+4
| | | | | | some feature flags in CPUID being set or cleared. ok pd
* vmm: support more than 3855MB guest memorymlarkin2017-08-051-3/+3
| | | | | | guest VMs can now use MAXDSIZ ram. ok deraadt@, stefan@, pd@
* Make max memory for VMs equal to MAXDSIZ to avoid failing later duringmlarkin2017-07-121-2/+2
| | | | | | VM setup. ok pd
* vmd: increase the max number of disks from 2 to 4. Requires kernel rebuildmlarkin2017-07-061-2/+2
| | | | | | as a struct passed to vmm has changed size. ok deraadt, pd
* event injection framework, will be used for other features coming shortlymlarkin2017-05-301-1/+3
| | | | ok deraadt
* FPU context save/restore for SVM in vmm(4), matches a previous diffmlarkin2017-05-301-1/+22
| | | | | | from a few weeks ago that did the same for Intel/VMX. ok deraadt
* rename some fieldsmlarkin2017-05-281-4/+4
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* Respect max VPID/ASID limits. VMX VPIDs are capped at 4095, for now.mlarkin2017-05-191-1/+2
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* Allow setting guest %xcr0 from vmd(8).mlarkin2017-05-051-2/+3
| | | | | | Tested on linux and amd64 OpenBSD guests. Posted to tech by Pratik Vyas.
* Allow setting of guest MSRs from vmd(8). This change is the first part ofmlarkin2017-05-021-2/+13
| | | | | | | | | | a larger effort to implement vmctl send/vmctl receive (snapshot and VM migration). From Pratik Vyas, Siri Chandana, Harshada Mone and Ashwin Agrawal, a group of students I am supervising. ok kettenis
* vmm: don't use invvpid if we didn't detect vpid capability duringmlarkin2017-04-281-1/+2
| | | | vcpu setup
* rename a struct that was denoted as "VMX only" to make it more clearmlarkin2017-04-271-6/+7
| | | | | | that it can be used in SVM and VMX. no functional change
* vmm(4): proper save/restore of FPU context during entry/exit.mlarkin2017-04-271-1/+12
| | | | | | | tested by reyk, dcoppa, and a few others. ok kettenis@ on the fpu bits ok deraadt@ on the vmm bits
* Bump the emulated PCI MMIO range end to 0xFFFFFFFF. This slightlymlarkin2017-03-231-2/+2
| | | | | | | | penalizes i386 guests who previously had memory allocated by vmd after 0xF0FFFFFF (the previous range end) but makes memory range calculation in vmd/mc146818 much much easier. This diff needs to be combined with the previous vmd diffs or you won't be able to create a vm with memory size larger than ~3855MB.
* SVM: asm support for SVM/RVImlarkin2017-02-201-1/+3
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* SVM: misspelled field name in vmcb struct (renamed to match SVM code I'mmlarkin2017-01-241-2/+2
| | | | merging)
* forgot this in previous commit (SVM_MSR* macro definitions)mlarkin2017-01-191-1/+5
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* rename a couple of macros that are causing me a merge headache with themlarkin2017-01-191-3/+3
| | | | next SVM diff
* SVM: vcpu_init_svm - allocate memory for control structures (vmcb,mlarkin2017-01-191-1/+7
| | | | msr bitmap, ioio bitmap, and host state save area)
* Starting to merge my old AMD SVM/RVI tree, piece by piece.mlarkin2017-01-131-1/+104
| | | | SVM/RVI: VMCB structure definitions for amd64/i386
* Remove vc_hsa_stack_va, it has not been used in a long time and is nomlarkin2017-01-121-2/+1
| | | | longer needed.
* SVM intercept codes (exit reason) definesmlarkin2017-01-111-1/+148
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* Don't use a bitfield in the msr store index structure. This may not end upmlarkin2016-10-261-3/+3
| | | | | initializing the unused bits, leading to VMABORTs during vmentry. Found the hard way on i386 vmm, but the problem could occur on amd64 as well.
* Allow 4 vio(4) interfaces in each VM. Also fix a bad interrupt assignment thatmlarkin2016-10-121-2/+2
| | | | | | | caused IRQ9 to be shared between the second disk device and the vio(4)s, which caused poor network performance. ok reyk, stefan
* add a debug function that was useful in finding the previousmlarkin2016-10-061-1/+6
| | | | broadwell/skylake bug.
* disable PAT and MTRR in guest VMsmlarkin2016-10-031-2/+2
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* Restrict MSR access to supported ones, log invalid accesses.mlarkin2016-09-041-1/+5
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* Make vcpu_reset_regs use new writeregs codestefan2016-09-011-28/+2
| | | | Makes reset code a little simpler. ok mlarkin@
* Add ioctls to get/set VCPU registersstefan2016-09-011-1/+60
| | | | ok mlarkin@
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