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2021-03-29Fix IA32_EPT_VPID_CAP_XO_TRANSLATIONS specificationdv1-2/+2
Per Intel SDM (Vol 3D, App. A.10) bit 0 should be read as a 1 if enabled. From Adam Steen. ok mlarkin@
2021-03-24The logic in mmrw() to check whether an address is within directbluhm1-4/+4
map was the wrong way around. The && prevented an EFAULT error and could pass userland addresses as kernel source to copyout(9). The kernel could crash with protection fault due to an invalid offset when reading /dev/kmem. Also make the range checks stricter. Not only the start address must be valid, but also the end address must be within the region to be copied. Note that sysctl kern.allowkmem=0 makes the bug unreachable by default. OK deraadt@
2021-03-19another unfortunate action to cope with relentless kernel growthderaadt1-2/+2
2021-03-17Always use an allocated buffer for {Read,Write}Blocks() to makeyasuoka2-80/+34
efid_io() simpler. Also fixes the problem on some machines when boot from CD-ROM. It happened because the previous version passed unaligned pointers to the functions even if it is restricted by the IoAlign property of the media. idea from kettenis, work with asou ok kettenis
2021-03-15Add acpi_iommu_device_map(), which replaces the DMA tag with one thatpatrick1-1/+7
is blessed with IOMMU magic, if available. This is mainly for arm64, since on amd64 and i386 the IOMMU only captures PCIe devices, as far as I know, which uses the pci_probe_device_hook(). This though is for non-PCI devices attached through ACPI. ok kettenis@
2021-03-11spellingjsg12-38/+38
2021-03-07Explicitly align kernel text.mortimer1-3/+3
lld11 no longer quietly aligns this when given an address, so we do the alignment explicitly. ok kettenis@
2021-02-23timecounting: use C99-style initialization for all timecounter structscheloha2-4/+18
The timecounter struct is large and I think it may change in the future. Changing it later will be easier if we use C99-style initialization for all timecounter structs. It also makes reading the code a bit easier. For reasons I cannot explain, switching to C99-style initialization sometimes changes the hash of the resulting object file, even though the resulting struct should be the same. So there is a binary change here, but only sometimes. No behavior should change in either case. I can't compile-test this everywhere but I have been staring at the diff for days now and I'm relatively confident this will not break compilation. Fingers crossed. ok gnezdo@
2021-02-13Fix a commentmlarkin1-2/+2
2021-02-13Remove trailing whitespacemlarkin1-14/+14
No code/functional change
2021-02-13Remove trailing whitespacemlarkin1-6/+6
No code/functional change
2021-02-09Activate use of PF_LOCK() by removing the WITH_PF_LOCK ifdefs.patrick1-2/+1
Silence from the network group ok sashan@
2021-02-04Add uhidpp(4), a driver for Logitech HID++ devices. Currently limited toanton1-1/+2
exposing battery sensors for HID++ 2.0 devices. Most of the code is derived from the hid-logitech-hidpp Linux driver. Thanks to Ville Valkonen <weezeldinga at gmail dot com> for testing. ok mglocker@
2021-02-04make if_pfsync.c a better friend with PF_LOCKsashan1-1/+2
The code delivered in this change is currently disabled. Brave souls may enable the code by adding -DWITH_PF_LOCK when building customized kernel. Big thanks goes to Hrvoje@ for providing test equipment and testing. As soon as we enter the next release cycle, the WITH_PF_LOCK will be defined as default option for MP kernels. OK dlg@
2021-01-28bios_memmap[] should not be a commonderaadt2-3/+4
ok kettenis
2021-01-28Again allow COPTS= to come from the environment again, and don't lose thederaadt1-4/+4
SMALL_KERNEL specific variations. ok espie jsg
2021-01-23Fix whitespace issuesmlarkin1-4/+4
2021-01-23vmm(4): wire faulted in pagesmlarkin1-20/+6
This change wires the pages used by virtual machines managed by vmm(4). When uvm swaps out a page, vmm(4) does not properly do TLB flushing, possibly leading to memory corruption or improper page access later. While this diff is not the correct fix (implementing proper TLB flush semantics), it does work around the problem by not letting the pages get swapped out in the first place. This means that under memory pressure, swap pages will have to come from other processes, and it also means you cannot overcommit vmm(4) memory assignment (eg, assign more memory to VMs than you actually have). It is my plan to fix this the correct way, but that will take time. This issue was originally pointed out a long time ago by Maxime V., but due to my taking a year away from OpenBSD, the issue remained unfixed.
2021-01-23introduce ujoy(4), a restricted subset of uhid(4) for gamecontrollers.thfr2-2/+5
This includes ujoy_hid_is_collection() to work around limitations of hid_is_collection() until this can be combined without fallout. input, testing with 8bitdo controller, and ok brynet@ PS4 controller testing, fix for hid_is_collection, and ok mglocker@
2021-01-03Allocate address space for reposting vga devices using km_alloc(9) ratherjmatthew1-7/+9
than uvm_km_valloc(9). ok kettenis@
2020-12-31remove pv includes which were missed in rev 1.70jsg1-6/+1
2020-12-28Sync with i386 by asserting that IPL values should be at least IPL_NONE.mpi1-1/+3
2020-12-27Enable acpihpet on install media, because otherwise clock initializationderaadt2-4/+4
is just too different from GENERIC or GENERIC.MP pointed out by jsg
2020-12-24handle reported core clock frequency of 0 on newer Intel Comet Lakejsg1-1/+3
The 'nominal core crystal clock frequency' from cpuid 0x15 is 0 on Intel model 0xa5 (CML-H CML-S62 CML-S102) and 0xa6 (CML-U62). So act as if 24 MHz was reported like we do on other Skylake/Kaby Lake variants. Comet Lake processors with model 0x8e (CML-U42 CML-Y42) use the same model number used by Kaby Lake and many other parts which was already handled. While we could approximate the crystal frequency with 'Processor Base Frequency' from cpuid 0x16 eax like FreeBSD and Linux do, kettenis@ couldn't get ntpd to sync a clock on a Skylake machine with: CPUID 0x15: eax=2, ebx=134, khz=0 CPUID 0x16: eax=1600, ebx=1600, ecx=100, edx=0 with reported crystal frequency changing from 24000 kHz to 23880 kHz (cpuid 0x16 eax * 1000 * cpuid 0x15 eax / cpuid 0x15 ebx) and TSC frequency changing from 1608000000 to 1599960000. Cannon Lake, Ice Lake, and Tiger Lake are known to return non-zero frequency in cpuid 0x15 so hopefully no other model ids have to be added. James Cook reported hangs on bsd.rd with i7-10710U 06-a6-00 (CML-U62) (which does not have acpihpet) but not with bsd.mp (which does) and has confirmed that both approaches fixed the problem.
2020-12-22stop showing amd l3 cache informationjsg2-27/+3
>= zen 2 based amd processors return a value of 9 for l3 cache assoc via cpuid 0x80000006. As that is a reserved value we end up incorrectly claiming the l3 cache is disabled. While it is possible to get l3 cache information via cpuid 0x8000001d when TOPEXT is advertised that will instead give information about the l3 cache available to the core complex (CCX) that the cpu belongs to where previously the amount of l3 available to all core complexes was shown. As we don't detail topology in dmesg or show the mapping of cores to core complexes just stop displaying l3 information. It already isn't shown on intel. ok gkoehler@
2020-12-20Convert uvm_km_valloc(9) calls to km_alloc(9). Tested in qemu withjmatthew1-3/+4
acpi disabled, no real mpbios hardware in sight. ok kettenis@
2020-12-16Do not clear useful bits in panic messages, always print full optebluhm1-19/+21
variable. Make PG_PVLIST panics consistent and print more values. OK mpi@
2020-12-13Turn simple sysctl_rdint into cpuctl_vars entriesgnezdo1-11/+8
ok gkoehler@
2020-12-09Use daddr_t and not daddr32_t in boot media.krw29-58/+58
At a minimum, amd64/i386 should now boot from 4TB GPT formatted disks. More daddr32_t terminations with extreme prejudice to follow. Tested by various, in snaps for a few days. ok deraadt@
2020-12-06Implement acpi_intr_disestablish() for amd64.kettenis1-1/+7
ok mpi@
2020-11-30reset fpu in fpu_kernel_enter() even when there is no xsave statejsg1-1/+3
Avoids the situation where FP code ran out of the amdgpu attachhook would sometimes trigger SSE FP exception traps because precision exceptions were not masked in mxcsr. feedback from and ok kettenis@
2020-11-28Since our IPI broadcast functions exclude the CPU doing the broadcast, wekettenis1-1/+2
need to explicitly call wbinvd() in wbinvd_on_all_cpus(). ok jsg@, deraadt@
2020-11-24Remove commented-out code messing with uvmexp.mpi1-40/+1
ok jca@
2020-11-15Add pchgpio(4), a driver for the GPIO controllers found on modern Intelkettenis1-1/+2
PCHs. With help from James Hastings. ok deraadt@
2020-11-13Delete unused #defines: T_USER hasn't been used since July 2018guenther1-8/+1
while TC_TSS and TC_FLAGMASK have _never_ been used ok kettenis@
2020-11-13Correct CVE number in commentguenther1-2/+2
2020-11-12Simplify interrupt entry stubs to not push around bogus trapno+errguenther1-29/+30
slots but rather go directly from the iretq frame to an intrframe. This saves 22 bytes in each of the 148 interrupt entry points. ok mpi@
2020-11-09Give sizes and types to more functions and objects.guenther2-7/+41
No effect on object code, just symbol table accuracy ok mpi@
2020-11-08In case of failure, call sigexit() from trapsignal instead of sensig().mpi1-5/+7
Simplify MD code and reduce the amount of recursion into the signal code which helps when dealing with locks. ok cheloha@, deraadt@
2020-11-03Give sizes to more of the functions in locore.Sguenther1-1/+15
ok mpi@
2020-11-03Correct comment typo in previousguenther1-2/+2
2020-11-02Restore abstraction of register saving into macros in frameasm.hguenther3-73/+79
The Meltdown mitigation work ran right across the previous abstractions; draw slightly different lines and use separate macros for interrupts vs traps vs syscall. The generated ASM for traps and general interrupts is completely unchanged; the ASM for the four directly routed interrupts is brought into line with the general interrupts; the ASM for syscalls is changed to delay reenabling interrupts until after all registers are saved and cleared. ok mpi@
2020-10-30Use a 64MB block to load the kernel to deal with kernel growth.kettenis2-4/+4
Note that the first 16MB of the block are currently unused since we link our kernels at physical address 0x01000000. Therefore 32MB is no longer enough to load a kernel that is now larger than 16MB. Fixes the "entry point at 0x10010000" hang that people have reported on some machines. ok patrick@, naddy@, deraadt@
2020-10-28Use "memory" on inline fence instructions to suggest to the compilerjsg1-4/+4
it shouldn't optimise across them. ok kettenis@
2020-10-27Adding IOMMU support for AMD Vi and Intel VTD (disabled)jordan3-5/+22
This creates separate domains for each PCI device and can provide protection against invalid memory access. Needed for Passthrough PCI from vmd. ok deraadt@, kettenis@ : ----------------------------------------------------------------------
2020-10-26Switch the pmap and PDP pools to IPL_VM, drop the PR_WAITOK flag from thekettenis1-4/+4
PDP pool and use the single page allocator for the PDP pool. This makes pmap_destroy(9) mpsafe while preventing additional pressure on the interrupt-safe kernel map. ok mpi@
2020-10-22uvm_grow() doesn't need KERNEL_LOCK anymore, and onfault never did.deraadt1-5/+4
minor refactorings to narrow KERNEL_LOCK just around uvm_fault() ok kettenis
2020-10-21Save and restore the MXCSR register and the FPU control word such thatkettenis1-1/+2
floating-point control modes are properly restored by longjmp(3). ok guenther@
2020-10-19the userland pagefault handler can drop the kernel lock before goingderaadt1-3/+2
into trapsignal() discussed with kettenis
2020-10-19deliver SIGSEGV rather than SIGBUS for T_PROTFLT,T_SEGNPFLT,T_STKFLT.deraadt1-5/+8
This is a similar translation as i386, and matches the idea that SIGBUS signals refer to problems with the underlying object rather than the mapping. ok kettenis
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