wireguard-openbsd - WireGuard implementation for the OpenBSD kernel

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Remove an #endif I forgot in there.	patrick	2013-05-02	1	-2/+1
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*	Add a driver for the secondary cache controller on the PandaBoard and	patrick	2013-05-02	2	-1/+302
\| \| \| \| \| \| \|	other ARM Cortex based boards. Disabled for now, until proper secondary cache flushing is done where it's needed. ok miod@
*	Add a secure monitor call function, so that a secondary cache controller	patrick	2013-05-01	1	-0/+29
\| \| \| \| \| \| \| \|	driver can talk to its controller properly. From drahn at dalerahn.com. ok bmercer@
*	Add a cortex bus which represents the ARM MPCore Complex.	patrick	2013-05-01	5	-0/+1177
	It will attach only to ARM Cortex A9 and A15 SoCs. The generic interrupt controller and timer will attach to this bus, later a secondary cache controller can be added. The base address for those controllers are figured out using the periphbase register. ok bmercer@