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* remove uneeded includes in md armv7 filesjsg2021-03-254-17/+4
| | | | based on include-what-you-use suggestions
* timecounting: use C99-style initialization for all timecounter structscheloha2021-02-232-4/+17
| | | | | | | | | | | | | | | | | | The timecounter struct is large and I think it may change in the future. Changing it later will be easier if we use C99-style initialization for all timecounter structs. It also makes reading the code a bit easier. For reasons I cannot explain, switching to C99-style initialization sometimes changes the hash of the resulting object file, even though the resulting struct should be the same. So there is a binary change here, but only sometimes. No behavior should change in either case. I can't compile-test this everywhere but I have been staring at the diff for days now and I'm relatively confident this will not break compilation. Fingers crossed. ok gnezdo@
* s/KHZ/kHz/ and reduce dmesg spam a bitkettenis2021-01-192-8/+8
| | | | ok tb@, deraadt@
* Extend the interrupt API on arm64 and armv7 to be able to pass aroundpatrick2020-07-142-20/+26
| | | | | | | | | | | | | | | | | | | | | | | | a struct cpu_info *. From a driver point of view the fdt_intr_establish_* API now also exist same functions with a *_cpu suffix. Internally the "old" functions now call their *_cpu counterparts, passing NULL as ci. NULL will be interpreted as primary CPU in the interrupt controller code. The internal framework for interrupt controllers has been changed so that the establish methods provided by an interrupt controller function always takes a struct cpu_info *. Some drivers, like imxgpio(4) and rkgpio(4), only have a single interrupt line for multiple pins. On those we simply disallow trying to establish an interrupt on a non-primary CPU, returning NULL. Since we do not have MP yet on armv7, all armv7 interrupt controllers do return NULL if an attempt is made to establish an interrupt on a different CPU. That said, so far there's no way this can happen. If we ever gain MP support, this is a reminder that the interrupt controller drivers have to be adjusted. Prompted by dlg@ ok kettenis@
* Use the full 32 bits for the miscellaneous armv7 timecounters.naddy2020-07-122-4/+4
| | | | | | | | | Checked against * ARM Architecture Reference Manual (agtimer) * ARM Cortex-A9 MPCore Technical Reference Manual (amptimer) * OMAP35x Applications Processor Technical Reference Manual (gptimer) Artturi Alm had independently suggested this in the past.
* Add support for timeconting in userland.pirofti2020-07-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This diff exposes parts of clock_gettime(2) and gettimeofday(2) to userland via libc eliberating processes from the need for a context switch everytime they want to count the passage of time. If a timecounter clock can be exposed to userland than it needs to set its tc_user member to a non-zero value. Tested with one or multiple counters per architecture. The timing data is shared through a pointer found in the new ELF auxiliary vector AUX_openbsd_timekeep containing timehands information that is frequently updated by the kernel. Timing differences between the last kernel update and the current time are adjusted in userland by the tc_get_timecount() function inside the MD usertc.c file. This permits a much more responsive environment, quite visible in browsers, office programs and gaming (apparently one is are able to fly in Minecraft now). Tested by robert@, sthen@, naddy@, kmos@, phessler@, and many others! OK from at least kettenis@, cheloha@, naddy@, sthen@
* Let the armv7 bus_dma layer and simplebus(4) implementation deal withkettenis2020-04-291-3/+2
| | | | | | | | | | | DMA remapping in the same way as arm64. This relies on the dma-ranges property in the device tree and allows us to get rid of the hack for the Raspberry Pi in the dwctwo(4) driver. Note that this does not include the hack in simplebus(4) that we have on arm64 since firmware that has the dma-ranges is in widespread use now. ok patrick@
* Add IPI support. Taken ftrom arm64.kettenis2019-09-291-2/+168
| | | | ok patrick@
* Enable interrupts while running interrupt handlers like we do on arm64.kettenis2019-09-251-3/+6
| | | | ok patrick@, jsg@
* Make the code that calculates the min/max priorities identical to the arm64kettenis2019-09-221-4/+4
| | | | | | | version. The divergence was probably an accident and the arm64 code makes more sense and is better tested. ok patrick@
* Reduce diffs to arm64 version of this. Mostly whitespace changes.kettenis2019-09-221-25/+24
| | | | No functional changes.
* For shared interrupts we need to make sure that we registerpatrick2018-12-071-7/+9
| | | | | | | | with the lowest IPL. Once we actually run the IRQ handler we raise to the highest IPL. Fixes a crash seen when having a network card in the PCIe slot of the MacchiatoBin. ok ccardenas@
* Use MAXCPUS as the number of elements for the array of per-cpu data.kettenis2018-08-111-4/+2
| | | | ok jsg@, patrick@
* Make it possible to build a MULTIPROCESSOR kernel on armv7. While thiskettenis2018-08-061-1/+18
| | | | | | | | doesn't actually spin up any secondary CPUs, it does run. Mostly a cleanup of <machine/cpu.h> along the lines of what I did earlier on arm64. Makes armv7 use the MI mplock implementation and implements copyin32. ok patrick@
* Implement ampintcmsi(4) in ampintc(4) to support MSI. The GICv2M is anpatrick2018-07-093-18/+180
| | | | | | | | | | | | | | | | | | | extension to the GIC controller, which is represented as subnode in the device tree. There can be multiple GICv2Ms, so it makes sense to attach those to ampintc(4) as some kind of simplebus. The GICv2M is simply an interrupt generator that can be used by PCIe devices to ring the door bell. There is no need for further configuration, we only need to find out which SPIs we are allowed to use for MSI and to register an edge triggered interrupt on a (randomly) allocated SPI. Implement support for interrupt types. The GIC only seems to support level triggered active-high or egdge triggered low-to-high interrupts. We currently always configure them to be level triggered, which is a sane default for most controllers. Since MSI interupts on the GIC are edge triggered, we need to be able to parse the type information and to configure the interrupt correspondingly. ok kettenis@
* Rename Debugger() into db_enter().mpi2017-04-301-2/+2
| | | | | | | Using a name with the 'db_' prefix makes it invisible from the dynamic profiler. ok deraadt@, kettenis@, visa@
* As a first step towards SMP, use an array for the destination masks withkettenis2017-03-211-21/+22
| | | | | | | | | | | | | | an element for each CPU. Use this mask directly instead of converting it into a cpu number and back into a mask again when routing interrupts. This avoids the need to handle uniprocessor systems in a special way as they will return 0 as the mask (the relevant register is defined as RAZ) and ignore what's written into the destination registers (the relevant registers are defined as WI). Future code that hatches the secondary CPUs will have to call into the driver to establish the masks for those CPUs. ok patrick@
* Record the target mask for the boot CPU when we attach and use that to pickkettenis2017-03-071-5/+13
| | | | | | | | the target CPU interface when establishing an interrupt. Makes interrupts work on machines that boot up on a CPU that is attached to a CPU interface that isn't zero. Discussed with Dale Rahn.
* There are 1023 possible values for the interrupts, but our masks limitpatrick2017-02-071-4/+4
| | | | | | | these currently to 255. Thus making it impossible to use higher IRQs than that. The AMD Seattle SoC though seems to provide 448 IRQs, which is kind of out of bounds, so raise them to the proper values. This makes interrupts work on that machine.
* Match on "arm,gic-400" another GICv2 compat string.jsg2016-12-241-1/+2
| | | | ok patrick@ kettenis@
* The code to retrieve the interrupt ID only works if the amount of IRQspatrick2016-12-231-3/+7
| | | | | | | | | supported by the controller is not too big. Otherwise the mask will be wrong and the calculated IRQ as well. Split the dynamic mask into two pieces. First of all use a static mask to remove the bits we don't want to look at. Then we use that value to check for spurious or false IRQs. ok jsg@
* Remove a couple of unsused static inline functions. Also remove a compariskettenis2016-09-241-11/+1
| | | | | | of an array to a null pointer that is always false. Found with clang. ok jsg@
* Before pmap7.c rev 1.35 and pmap.h rev 1.44 DMA'able memory with thejsg2016-08-221-1/+13
| | | | | | | | | | | | | | | | | | | BUS_DMA_COHERENT flag was mapped as device memory which does not use the store buffer. It is now mapped as normal inner and outer non-cacheable which does. While we drain the cpu store buffer for this case, on cortex a9 systems we also need to explicitly drain the PL310 L2's store buffer. With PL310 revisions r3p2 and later this is done automatically after being present in the store buffer for 256 cycles. On i.MX6 PL310 is rev r3p1 which does not have this behaviour. This issue is i.MX6 errata ERR055199 and PL310 errata 769419. This change restores io performance with a usb flash drive attached to my cubox. Raw reads go from 3 MB/s to 19 MB/s for example. Based on code written by patrick@ some time ago. ok kettenis@ patrick@
* Remove the remains of a workaround to get GIC ranges for exynos.jsg2016-08-211-3/+1
| | | | | | Exynos differed from everything else by not having GIC at fixed offsets from PERIPHBASE. Now that ampintc/GIC attaches using FDT we get the ranges out of the FDT instead of using offsets from PERIPHBASE.
* Dynamically attach agtimer(4). Since agtimer(4) also provides the delay()kettenis2016-08-102-43/+53
| | | | | | | | | | function for platforms that have it, rework the code a bit such that it can be used before agtimer(4) attaches. Introduce a new agtimer_init() function that checks whether the CPU implements the Generic Timer feature and switches to agtimer_delay() if that feature is present. Call this function from the generic platform initialization code. ok jsg@
* Always allocate intrhand with M_WAITOK.patrick2016-08-061-6/+2
| | | | Requested by and ok kettenis@
* Extend the interrupt controller API with a disestablish functionality.patrick2016-08-061-1/+2
| | | | | | | This will be helpful for interrupt combiner that need to re-establish their main interrupt when their interrupt priorities change. ok kettenis@
* Rework ampintc's interrupt disestablish code to make it actually dopatrick2016-08-061-8/+16
| | | | | | | its job. Recalculate the mask after the handler is taken from the list to properly set the new prioritization. ok kettenis@
* Unmask the timer output signal for real.kettenis2016-08-051-3/+3
| | | | ok patrick@, jsg@
* Dynamically attach ampintc(4) and make it register itself as an interruptkettenis2016-08-042-68/+76
| | | | | | | | | | | | | | | controller. Switch all i.MX6 devices over to the new FDT-aware interrupt establish API and enable imxgpc(4). This may break other platforms that use ampintc(4) as their interrupt controller. We will fix this as soon as possible by switching them over to the new interrupt establish API as well. This also removes the hack in fec(4) to avoid the gpio-based interrupt workaround. This commit is an essential step on the road to fix that issue properly. ok patrick@, jsg@
* Rework mainbus and implement simplebus to be able to span a tree-likepatrick2016-05-022-4/+4
| | | | | | | topology based on device tree information. Introduce a common attach args structure to be used for all fdt-capable bus devices. ok jsg@ kettenis@
* Fix match function so that the cortex bus only attaches if the attachpatrick2016-04-081-2/+8
| | | | | | args are actually looking for the cortex bus. ok kettenis@
* Switch from PSR_X_bit and X32_bit PSR macro names to just PSR_X.jsg2016-01-311-5/+5
| | | | | This matches FreeBSD and makes things a bit more consistent. Discussed with Patrick.
* comment typommcc2015-12-122-4/+4
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* Fix build with DEBUG_INTC defined; from Daniel Bolgheroni on tech@miod2015-11-051-10/+4
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* The exynos gic is not at a fixed offset from periphbase unlikejsg2015-07-151-1/+13
| | | | | | | the other socs. Handle this by setting variables in exynos{4,5}_init functions and calling the board_init callback earlier. tested by and ok bmercer@
* Add some changes from Patrick Wildt in bitrig that are required to makejsg2015-06-061-8/+7
| | | | | | | | | the qemu cortex a15 useable without trustzone. Establish the interrupt for the non-secure physical timer (30), in addition to the secure physical timer (29). Stop masking the timer output signal in the interrupt handler.
* add some more cortex A idsjsg2015-05-293-6/+9
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* Remove unused bus space tags/handles. The generic timer uses the cp15jsg2015-05-291-11/+1
| | | | coprocessor space.
* ARM L2C driver is only relevant on Cortex-A9 machines.jsg2015-05-201-2/+5
| | | | From Patrick Wildt in bitrig.
* yet more mallocarray() changes.doug2014-12-131-4/+3
| | | | ok tedu@ deraadt@
* Add offsets for cortex-A7/A15. Adapted from bitrig.rapha2014-10-081-5/+21
| | | | ok jsg@ bmercer@
* add a size argument to free. will be used soon, but for now default to 0.tedu2014-07-121-2/+2
| | | | after discussions with beck deraadt kettenis.
* Support for the ARM Generic Timer used in the Cortex-A7 and Cortex-A15.patrick2013-09-092-1/+413
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* Instead of printing on spurious interrupts, use an event counter to showpatrick2013-09-061-2/+5
| | | | how many of those there have been.
* Remove duplicate loop.rapha2013-08-081-6/+1
| | | | ok patrick@
* The Cortex bus should be useful for Cortex-A7, too.patrick2013-08-061-2/+3
| | | | ok rapha@ jsg@
* Attach amptimer only on Cortex-A9, as all Cortex-A8 doesn't have a genericpatrick2013-08-061-2/+5
| | | | | | timer and the newer Cortexes have another generic timer. ok rapha@ jsg@
* Don't pull cpufunc.h in from the machine include directory, but frompatrick2013-06-141-2/+2
| | | | | | the arm one. ok bmercer@
* Have the ARM MPCore Timer use the private timer, which will be very usefulpatrick2013-05-091-30/+117
| | | | | | | for SMP on the newer ARMv7 boards. From drahn at dalerahn.com. ok bmercer@
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