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path: root/sys/arch/octeon/dev/cn30xxuart.c (follow)
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* Ensure proper order of register accesses by readback after write.visa2017-09-211-2/+5
* Attach com(4) using fdt on octeon.visa2017-07-031-50/+74
* Enable UART FIFOs.visa2016-04-141-2/+5
* Wrap comintr() so that the interrupt handler always returns non-zero.visa2016-04-141-2/+17
* Whitespace.uebayasi2015-02-051-7/+7
* Use octeon_xkphys_*_8().uebayasi2015-02-051-21/+16
* The io clock on Octeon II (CN6xxx) runs at a different rate to the cpu clock.jmatthew2014-06-171-2/+3
* add XXX comment for delay_changed, untill we figure out what it actually does.jasper2013-06-051-1/+2
* whitespacejasper2013-06-051-4/+4
* remove unneeded octeonreg.h includejasper2013-06-021-2/+1
* combus renamed uartbus, com_oct renamed cn30xxuartsyuu2011-05-081-0/+211