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* Add a driver for OCTEON two-wire serial interface.visa2019-04-231-0/+438
| | | | Not enabled yet because of a conflict with octrtc(4).
* Remove an unused header.visa2019-03-211-60/+0
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* Remember to detach the event counter when disestablishingvisa2019-03-172-2/+4
| | | | an interrupt handler.
* Replace a hand-rolled linked list with SLIST.visa2019-03-171-32/+37
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* Let each interrupt controller driver choose how to implementvisa2019-03-174-7/+45
| | | | | | | intr_barrier(9). With this change, the barrier should finally work properly with cnmac(4) interrupts that have been assigned to secondary cores.
* Move intr_barrier(9) to the platform level so that it can be customized.visa2019-03-171-1/+7
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* Unify the top-level structure of interrupt handles. This helpsvisa2019-03-161-8/+26
| | | | when implementing interrupt-specific logic for intr_barrier(9).
* Fix incorrect flag.visa2019-03-161-2/+2
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* Include header <sys/evcount.h> where event counters are used, so thatvisa2019-03-163-3/+6
| | | | header <machine/intr.h> can eventually stop including it on octeon.
* Use a locally defined intrhand in octciu.c to ease future changes.visa2019-03-151-9/+23
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* Fix the balancing of work queue interrupts.visa2019-03-141-2/+2
| | | | | | | | | | | | | | | The value of `ncpusfound' no longer reflects the number of cores that will be utilized by the kernel; it can be larger if secondary cores have not been enabled by the firmware. This can lead to incorrect assignment of work queue interrupts, making certain cnmac(4) ports unable to receive packets. This is a regression introduced in r1.108 of octeon/machdep.c. Correct the problem by using `ncpus' for the balancing. All secondary cores have been attached and the value is final by the time work queue interrupt handlers are set up. Network issue reported by krw@
* Use SMR instead of reference counting for session reclamation.visa2019-03-101-17/+25
| | | | | This reduces the need of atomic operations. The lookup tree still requires serialization, though.
* Handle card detect GPIO.visa2019-01-131-1/+14
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* Pass timeout in seconds instead of ticks.visa2019-01-131-5/+4
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* Add a driver for OCTEON GPIO controller.visa2019-01-121-0/+192
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* Attach the AHCI controller bridge driver even if the AHCI controllervisa2019-01-121-9/+13
| | | | node is not present in fdt.
* tweak ohci_checkrev so it doesnt print a leading comma and space.dlg2019-01-071-1/+3
| | | | | | | | | it assumes that it always followed an interrupt string, but we don't print that on fdt. having the bus responsible for the whitespace means the fdt glue can print a colon to separate the bus info from checkrev output, while every other glue keeps the comma. ok deraadt@
* match arm64 and armv7 and print unconfigured simplebus devices on octeonjsg2019-01-051-2/+23
| | | | ok and tested by visa@
* Fix .end symbol.visa2019-01-031-2/+2
| | | | From Mikhael Skvortsov
* Fix pool ipl to prevent a deadlock scenario.visa2018-12-161-2/+2
| | | | | While here, make the pool use the default memory alignment. The default setting is good enough for the driver and the hardware.
* Make octeon kernels compile with DEBUG.visa2018-06-131-2/+2
| | | | Based on a diff from jj@. Thank you!
* Add sizes for free() for octeon.fcambus2018-05-302-7/+7
| | | | OK deraadt@, visa@
* replace add_*_randomness with enqueue_randomness()jasper2018-04-281-2/+2
| | | | | | | | | this gets rid of the source annotation which doesn't really add anything other than adding complexitiy. randomess is generally good enough that the few extra bits that the source type would add are not worth it. ok mikeb@ deraadt@
* Add a driver for the OCTEON cryptographic unit. It providesvisa2018-04-093-1/+1862
| | | | | | | | | | | | | | | | | | | a hardware-accelerated implementation of several encryption and authentication algorithms for ipsec(4): AES-CBC AES-CTR AES-GCM AES-GMAC HMAC-MD5 HMAC-SHA1 HMAC-SHA2-256 HMAC-SHA2-384 HMAC-SHA2-512 Please note that the driver is currently disabled. OK deraadt@
* Fix reference clock frequency.visa2018-03-021-3/+3
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* Declare ci_ipl volatile to prevent the compiler from optimizingvisa2018-02-242-22/+2
| | | | | | | | | | | | | | | | | | or reordering accesses to the variable. Assume that the assembler preserves the correct sequence of instructions, which allows the removal of the explicit noreorder/reorder toggles from the C code. With ci_ipl being volatile, drop mips_sync() calls that follow the accesses of the variable. The sync is redundant as a compiler barrier. In addition, the MIPS64 CPU designs should not need the sync for pipeline or write buffer control. According to miod@, the use of the instruction is a carryover from code targeting early MIPS designs that lack tight integration with the cache and write buffer. Discussed with and testing help from miod@. Tested on CN5020, CN6120, CN7130, CN7360, Loongson 2F and 3A1000, R4400, R8000, R10000 and R16000.
* Always lock the kernel lock with non-MP-safe interrupt handlers.visa2018-01-232-4/+4
| | | | Suggested by kettenis@
* Fix bit.visa2018-01-161-2/+2
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* Fix return value.visa2018-01-161-2/+2
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* Assume that direct-mapped addresses come from the xkphys segment.visa2018-01-071-11/+4
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* Add references to errata.visa2018-01-072-11/+13
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* Don't pull in <sys/file.h> just to get fcntl.hguenther2017-12-302-4/+4
| | | | ok deraadt@ krw@
* Make octeon_intr_establish() assume edge triggering with CIU3.visa2017-12-271-2/+3
| | | | This makes the API usable with edge triggered interrupt sources.
* Ensure interrupt delivery is disabled when setting interruptvisa2017-12-271-1/+3
| | | | delivery entry.
* Show board ID and revision in dmesg to ease the identificationvisa2017-12-051-2/+4
| | | | | | of system model. The early boot code already prints them, but that output is not buffered and tends to be left out from dmesg submissions.
* Drop cn30xxpow_intr_establish(), cn30xxpow_intr() and some othervisa2017-12-052-144/+2
| | | | unused code. POW interrupts are now handled in if_cnmac.c.
* On wqe error, show also word2 and word3. Those might help in debugging.visa2017-11-261-1/+3
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* Initialize Rx subsystems before enabling the processing of incomingvisa2017-11-261-4/+4
| | | | | | | | packets. Otherwise, a skosh of traffic may be handled using hardware default settings. One of the consequences is that packets can end up into a wrong POW group, causing a panic in cnmac_intr(). Panic reported by and testing help from Janne Johansson
* Add the board ID of the Unifi Security Gateway PRO-4.visa2017-11-201-1/+2
| | | | Not tested with the hardware.
* Fix the product code of the Unifi Security Gateway.visa2017-11-203-6/+6
| | | | Prompted by Justin Hibbits
* Submit incoming packets to the network stack in batches like is donevisa2017-11-181-25/+19
| | | | in many other NIC drivers. This reduces submission overhead.
* Move the packet input work requesting inside if_cnmac.c. This removesvisa2017-11-183-52/+74
| | | | a layer of abstraction that would complicate upcoming changes.
* Pass the software context as an argument to the interrupt handler.visa2017-11-181-19/+15
| | | | | This is now possible because each port has a dedicated work queue interrupt.
* Rename octeon_eth_* to cnmac_* for consistency with the driver's name.visa2017-11-182-229/+220
| | | | This also makes the code a bit less noisy to read.
* Add the board ID for the Ubiquiti Unifi Security Gateway.visa2017-11-183-3/+6
| | | | From Justin Hibbits, thanks!
* Synchronize command initiation, event wait, and interrupt handlingvisa2017-11-091-5/+21
| | | | | | using a mutex. This lets octmmc_intr() run without the KERNEL_LOCK(). Tested on CN6120, CN7130 and CN7360.
* Set the core's own group mask when scheduling work, to receive workvisa2017-11-052-5/+5
| | | | from the intended group.
* Handle failure.visa2017-11-051-3/+4
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* slight cleanupvisa2017-11-051-22/+3
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* Remove unmaintained debug code.visa2017-11-0510-1466/+12
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