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* Attach com(4) using fdt on octeon.visa2017-07-031-1/+3
| | | | | The relevant part of uartbus(4) is made part of the com(4) glue to avoid extra maneuvers in the code.
* Fix the timecounter register on CN72xx/CN73xx.visa2017-06-191-1/+3
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* There is no RTC on the E1000 board.visa2017-06-191-1/+2
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* Split octeon interrupt code into a glue layer and a CIU driver.visa2017-06-181-2/+23
| | | | | | | This makes possible to add drivers for other interrupt controllers on the platform. The glue layer has been derived from arm64/armv7.
* Drop unnecessary call to octeon_setintrmask(). The function gets calledvisa2017-06-181-2/+1
| | | | by the splx() handler.
* Define register_splx_handler() in one place.visa2017-06-111-13/+2
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* add a BUS_DMA_64BIT flag to bus_dma on all our archs.dlg2017-05-081-1/+2
| | | | | | | | | this is so drivers can advertise that they can handle 64 dma addresses to the platform. it may choose to handle dmamaps differently based on this flag. tweaks and ok tom@ ok kettenis@
* Add prid for CN72xx/CN73xx.visa2017-04-071-1/+2
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* Make SoC version available in a simple form.visa2017-04-071-1/+7
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* Extend the fdt interrupt API a little.visa2017-04-061-3/+7
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* Define cache line size for the per-cpu API.visa2017-02-261-1/+3
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* Fix IO clock speed and system reset on Octeon III.visa2016-12-172-2/+11
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* There is no RTC on Shasta, so do not attach the driver.visa2016-12-171-1/+2
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* Add a routine for setting up interrupt handlers using fdt.visa2016-12-081-1/+3
| | | | ok kettenis@
* Add fdt_attach_args and simplebus for implementing fdt-capablevisa2016-12-081-0/+37
| | | | | | drivers on octeon. Adapted from armv7. ok kettenis@
* Make PHY address lookups fail instead of using CAM-0100 entriesvisa2016-10-291-1/+2
| | | | when the system board is unhandled.
* Add $OpenBSD$ / replace $Id$ with $OpenBSD$.visa2016-07-161-1/+1
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* Remove octeon_disable_interrupt() and octeon_restore_status().visa2016-07-161-45/+1
| | | | | | They are unused and equivalent to disableintr() and setsr(). While here, clean up a few other leftovers.
* Use the synciobdma instruction instead of the sync instruction forvisa2016-07-101-1/+11
| | | | | | | flushing any pending local IOBDMA operations. The sync instruction is overkill because it implies a full memory barrier. ok jasper@ (long time ago)
* Add openprom(4) for octeon.visa2016-07-052-1/+72
| | | | ok kettenis@ deraadt@ jasper@
* Add fdt init for octeon.visa2016-07-011-1/+3
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* Add support for the second GMX interface on Octeon II. This enablesvisa2016-06-221-13/+2
| | | | | | | ports eth[0-3] on 8-port EdgeRouters. Currently, port eth0 maps to network interface cnmac4, eth1 to cnmac5 etc. ok dlg@, tested by martijn@
* Fill the packet data pool with standard mbuf clusters instead ofvisa2016-05-301-2/+2
| | | | | | | driver-specific memory blocks. This lets the cnmac(4) RX path run without an mbuf ext_free callback. ok uebayasi@
* Reduce the size of gather buffers and allocate more of them to makevisa2016-05-241-3/+3
| | | | | | | better use of memory. This should prevent gather buffer starvation on currently supported systems. Discussed with mpi@
* Initial support for MSI-X. Only supported on amd64 for now. I have diffs tokettenis2016-05-041-1/+2
| | | | | | | | | | actually use this in em(4) and xhci(4), but I'm not committing those yet because we almost certainly need to save and restore the MSI-X registers during suspend/resume. However, this allows mpi@ to play with multiple-vector support in networking hardware. Requested by mpi@ ok mlarkin@, mikeb@
* On Octeon systems, U-Boot provides a list of usable memory regions. Usevisa2016-03-211-1/+19
| | | | | | | | the list instead of hardcoded regions in memory setup. Works on EdgeRouter Lite, EdgeRouter Pro, Lanner MR326b and Movidis 16x. Tested by jj@ Tested by and ok jmatthew@
* Rename mips64's trap_frame into trapframe.mpi2016-03-061-3/+3
| | | | | | For coherency with other archs and in order to use it in MI code. ok visa@, tobiasu@
* Some implementations of HitSyncDCache() call pmap_extract() for va->pavisa2016-01-051-1/+3
| | | | | | | | | | | | | | | | | | conversion. Because pmap_extract() acquires the PTE mutex, a "locking against myself" panic is triggered if the cache routine gets called in a context where the mutex is already held. In the pmap, all calls to HitSyncDCache() are for a whole page. Add a new cache routine, HitSyncDCachePage(), which gets both the va and the pa of a page. This removes the need of the va->pa conversion. The new routine has the same signature as SyncDCachePage(), allowing reuse of the same routine for cache implementations that do not need differences between "Hit" and non-"Hit" routines. With the diff, POWER Indigo2 R8000 boots multiuser again. Tested on sgi GENERIC-IP27.MP and octeon GENERIC.MP, too. Diff from miod@, ok kettenis@
* Use #ifndef _MACHINE_DISKLABEL_H_ everywhere. Replace _ARM_DISKLABEL_H_krw2015-09-301-1/+6
| | | | | | and _SH_DISKLABEL_H_ with _MACHINE_DISKLABEL_H_. Add the guard to loongson and octeon. The #defines are not used anywhere else in the tree so no functional change.
* Use consistant whitespace/comments for #define'ing LABELSECTOR,krw2015-09-301-4/+4
| | | | | LABELOFFSET and MAXPARTITIONS. Easier on the eye when scanning through all these files. No functional change.
* Let MP-safe interrupt handlers run without the kernel lock on octeon.visa2015-09-261-2/+3
| | | | ok kettenis@
* intr_barrier(9) for loongson, octeon and sgi.kettenis2015-09-131-1/+3
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* The mplock implementations on MP-enabled mips64 platforms, octeon andvisa2015-09-091-51/+2
| | | | | | | sgi, are identical. Put one implementation in mips64 and drop the platform-specific copies, to remove duplicated code. ok miod@
* Add a new flash driver for Octeon that allows access to the internalpirofti2015-07-202-2/+4
| | | | | | | | | | | | | | | memory on (at least) D-Link DSR500 machines. This follows the CFI specification with code borrowed from zrouter (FreeBSD). The idea, once the current driver is thoroughly tested, would be to move it to MI land. The prerequisites to MI are width, shift and row detection and handling. In the long run I hope to be able to also add wdc support. For now write support is disabled. Okay miod@, deraadt@.
* Remove {LOAD,COUNT}_TEXTA from libsa loadfile, it only made sense for a.outmiod2015-07-171-3/+3
| | | | kernels and we no longer have any.
* Ditch the octeon simulator non-sense.pirofti2015-07-151-2/+1
| | | | Discussed with miod@.
* unify the mutex implementations on all the mips64 platforms.dlg2015-07-082-59/+5
| | | | | | | | this basically copies the sgi implementation to mips64 and removes it from the rest. this way they get an optimised UP mutex implementation and correct asserts on all platforms. ok miod@ jmatthew@
* - add board type of edgerouter projasper2014-10-261-6/+4
| | | | | | | | | - don't attach octrtc on the edgerouter pro either openbsd boots fine on this system, but as there's no ethernet support yet there's no storage at all right now. ok pirofti@
* define octeon model cn61xx pass 1.1jasper2014-10-261-1/+2
| | | | ok pirofti@
* Lower VM_PHYSSEG_MAX from the mips64 default to a generous 4, and changemiod2014-08-121-1/+9
| | | | allocation strategy to VM_PSTRAT_BIGFIRST.
* Remove evcnt and %b format strings relying upon SEIL extensions. This givesmiod2014-08-111-44/+1
| | | | | OCTEON_ETH_DEBUG kernels a chance to build. No functional change for regular kernels.
* whitespacejasper2014-07-142-40/+40
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* add guards to just make available to the bootblocks what they need.jasper2014-07-121-2/+4
| | | | prompted by miod@
* Add ffs routine needed for upcoming octhci interrupt routine.pirofti2014-07-091-1/+14
| | | | Okay miod@
* The io clock on Octeon II (CN6xxx) runs at a different rate to the cpu clock.jmatthew2014-06-173-3/+13
| | | | | | Program the uarts based on the io clock rate on these platforms. ok jasper@ pirofti@ yasuoka@
* Due the virtually indexed nature of the L1 instruction cache on most mipsmiod2014-03-311-3/+7
| | | | | | | | | | | | | | | | | | | | processors, every time a new text page is mapped in a pmap, the L1 I$ is flushed for the va spanned by this page. Since we map pages of our binaries upon demand, as they get faulted in, but uvm_fault() tries to map the few neighbour pages, this can end up in a bunch of pmap_enter() calls in a row, for executable mappings. If the L1 I$ is small enough, this can cause the whole L1 I$ cache to be flushed several times. Change pmap_enter() to postpone these flushes by only registering the pending flushes, and have pmap_update() perform them. The cpu-specific cache code can then optimize this to avoid unnecessary operations. Tested on R4000SC, R4600SC, R5000SC, RM7000, R10000 with 4KB and 16KB page sizes (coherent and non-coherent designs), and Loongson 2F by mikeb@ and me. Should not affect anything on Octeon since there is no way to flush a subset of I$ anyway.
* It's been a quarter century: we can assume volatile is present with that name.guenther2014-03-292-7/+7
| | | | ok dlg@ mpi@ deraadt@
* Support BUS_DMA_NOCACHE in bus_dma(9). Memory allocations done withmiod2014-03-101-14/+15
| | | | | | BUS_DMA_NOCACHE (or BUS_DMA_COHERENT if the platform does not have coherent caches) will use PMAP_NOCACHE when invoking pmap_enter(), to avoid creating cached mappings, and then evicting them from the cache.
* Rework the per-cpu cache information. Use a common struct to store the linemiod2014-03-091-2/+5
| | | | | | | size, the number of sets, and the total size (and the set size, for convenience) per cache (I$, D$, L2, L3). This allows cpu.c to print the number of ways (sets) of L2 and L3 caches from the cache information, rather than hardcoding this from the processor type.
* Add a stub for the new MD hook needed to handle ACPI Power Resources.mpi2013-11-051-1/+2
| | | | ok kettenis@
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