summaryrefslogtreecommitdiffstats
path: root/sys/arch/octeon (follow)
Commit message (Collapse)AuthorAgeFilesLines
* spellingjsg2021-03-117-17/+17
|
* Add initial bits for Check Point UTM-1 EDGE N.visa2021-03-093-3/+15
| | | | From Thaison Nguyen
* Tweak whitespace and adjust prototypes.visa2021-03-041-23/+21
|
* Combine octeon_pcibusvar.h into octeon_pcibus.c to reduce scatter.visa2021-03-042-56/+9
|
* we don't have to cast to caddr_t when calling m_copydata anymore.dlg2021-02-251-6/+4
| | | | | | | | | | | | | | | | the first cut of this diff was made with coccinelle using this spatch: @rule@ type caddr_t; expression m, off, len, cp; @@ -m_copydata(m, off, len, (caddr_t)cp) +m_copydata(m, off, len, cp) i had fix it's opinionated idea of formatting by hand though, so i'm not sure it was worth it. ok deraadt@ bluhm@
* Fix disestablishing of PCI interrupt handlers.visa2021-02-201-9/+2
|
* Do not reprogram address filter after MII status changevisa2021-02-171-5/+1
| | | | | The address filter is not affected by link parameter changes, so its reprogramming can be skipped.
* Revise cnmac(4)'s address filter setupvisa2021-02-134-114/+47
| | | | | | | | | Set up the DMAC filter in one go instead of doing it separately for unicast and multicast DMACs. This attempts to make the code a little more readable. The setup should now run a bit faster as well because it now does fewer register accesses. Tested on CN5020, CN6120 and CN7130.
* Leave out gp initialization from kernel entry on mips64visa2021-02-112-5/+2
| | | | | | | | | On OpenBSD/mips64, the kernel is compiled with -mno-abicalls. This disables gp-relative addressing and essentially makes gp a spare register in the kernel. Hence it is unnecessary to initialize gp when entering the kernel. The _gp symbol is not needed either. Suggested by miod@
* Revise kernel's ld.script on octeonvisa2021-02-063-13/+56
| | | | | | | | | This allows more control over the structure of the linked kernel image. Now the ELF .openbsd.randomdata segment can be omitted from BOOT kernel. The segment has caused trouble with broken firmware when the firmware tries to load it on top of the actual kernel segment. Discussed with and OK deraadt@
* Add uhidpp(4), a driver for Logitech HID++ devices. Currently limited toanton2021-02-041-1/+2
| | | | | | | | | exposing battery sensors for HID++ 2.0 devices. Most of the code is derived from the hid-logitech-hidpp Linux driver. Thanks to Ville Valkonen <weezeldinga at gmail dot com> for testing. ok mglocker@
* Handle Netgear ProSecure UTM25visa2021-02-044-4/+26
| | | | | | | | | | | This makes the system recognize and configure Netgear ProSecure UTM25. Of the network ports, LAN1-4 and WAN1 are functional. WAN2 does not work for some reason. Even though WAN1 has a separate link to the SoC, the connection appears to go through the same switch that the LAN ports use. At the moment, the system relies on U-Boot to set up the switch so that the LAN and WAN segments stay separate. Initial diff and input from Thaison Nguyen, thank you!
* Abstract octeon board handling a littlevisa2021-01-306-39/+75
| | | | | | | Detect octeon board model in one place, and replace firmware-supplied board_type with an abstract model identifier in driver code. This makes it easier to manage with different products, and board flavours, that happen to use the same model information, such as board_type.
* Again allow COPTS= to come from the environment again, and don't lose thederaadt2021-01-281-4/+4
| | | | | SMALL_KERNEL specific variations. ok espie jsg
* introduce ujoy(4), a restricted subset of uhid(4) for gamecontrollers.thfr2021-01-232-2/+5
| | | | | | | | This includes ujoy_hid_is_collection() to work around limitations of hid_is_collection() until this can be combined without fallout. input, testing with 8bitdo controller, and ok brynet@ PS4 controller testing, fix for hid_is_collection, and ok mglocker@
* Add kstat to ogx(4).visa2021-01-012-9/+404
|
* Enable IPv4 and TCP/UDP checksum offload on transmission.visa2020-12-312-11/+53
|
* Rename the macro MCLGETI to MCLGETL and removes the dead parameter ifp.jan2020-12-122-4/+4
| | | | | | OK dlg@, bluhm@ No Opinion mpi@ Not against it claudio@
* Use daddr_t and not daddr32_t in boot media.krw2020-12-091-2/+2
| | | | | | | | | | At a minimum, amd64/i386 should now boot from 4TB GPT formatted disks. More daddr32_t terminations with extreme prejudice to follow. Tested by various, in snaps for a few days. ok deraadt@
* Revert accidental commit.visa2020-10-251-2/+1
|
* Add missing firmload attribute.visa2020-10-252-3/+4
|
* Remove unnecessary count of device instances.visa2020-10-101-2/+2
|
* Add I2C bus scan routine for octiic(4)visa2020-09-101-1/+34
| | | | | | Unfortunately, machines tend to come with underpopulated device trees, and consequently this change is not very useful as is. The lack of good data is troublesome especially with things like I2C bus switches.
* Register octiic(4) with the I2C frameworkvisa2020-09-101-5/+12
| | | | | This generally is an exercise in futility because the phandle of the controller node tends to be missing.
* Make ogx(4)'s outbound bpf(4) tap actually workvisa2020-09-091-1/+7
|
* Clean up attachment of octgmx(4) a bitvisa2020-09-081-54/+39
|
* Handle AGL interfacevisa2020-09-086-19/+366
| | | | This makes certain machines' management network port usable.
* Add kstat to cnmac(4)visa2020-09-048-91/+353
| | | | | | | | | | This makes various receive and transmit event counters readable. This additionally replaces the old, and somewhat unusual, way of updating error counters in ifp. Most of the hardware counters are 32 bits wide. Hence the code polls them periodically and adds the values to 64-bit software counters. The hardware counters are cleared when read.
* vfs_shutdown() is neccessary to ensure buffer cache drain before reexec()deraadt2020-09-021-1/+4
| | | | ok kettenis visa
* Make fdt root node's model property readable through sysctl hw.productvisa2020-08-281-2/+19
|
* Remove unused headersvisa2020-08-151-6/+1
|
* Inline handling of receive checksum offloadvisa2020-08-153-34/+17
|
* Suppress kernel printf output in the octeon boot kernel.visa2020-07-241-1/+3
| | | | OK kettenis@
* Userland timecounter implementation for octeonvisa2020-07-182-3/+7
| | | | OK naddy@; no objections from kettenis@
* Synchronize each core's CP0 cycle counter using the IO clock counter.visa2020-07-113-4/+95
| | | | | | | | | | | This makes the cycle counter usable as timecounter on multiprocessor machines. Idea from Linux. Tested on CN5020, CN6120, CN7130 and CN7360. Looks reasonable to kettenis@
* Change users of IFQ_SET_MAXLEN() and IFQ_IS_EMPTY() to use the "new" API.patrick2020-07-101-2/+2
| | | | ok dlg@ tobhe@
* Make membar_consumer() a plain compiler barrier in kernel on octeon.visa2020-07-081-1/+2
| | | | | | | | | | | The processor does not perform speculative reads and only one of its execution pipes should issue memory accesses. As a result, loads should happen in the correct order without barrier instructions. Tested on CN5020, CN6120, CN7130 and CN7360. This diff has been in use on the octeon-based mips64 bulk build cluster for several months. Also tested in snaps for a while.
* IEEE1275 (Open Firmware) defines that parameter name strings can have akettenis2020-07-061-53/+11
| | | | | | | | | | | | | | | | | | | | | | length of up to 31 characters. This limit is also present in the flattened device tree specification/ Unfortunately this limit isn't enforced by the tooling and there are systems in the wild that use longer strings. This includes the device trees used on POWER9 systems and has been seen on some ARM systems as well. So bump the buffer size from 32 bytes (31 + terminating NUL) to 64 bytes. Centrally define OFMAXPARAM to this value (in <dev/ofw/openfirm.h>) replacing the various OPROMMAXPARAM definition scattered around the tree to make sure the FDT implementation of OF_nextprop() uses the same buffer size as its consumers. Eliminate the static buffer in various openprom(4) implementations on FDT systems. Makes it possible to dump the full device tree on POWER9 systems using eeprom -p. ok deraadt@, visa@
* Add support for timeconting in userland.pirofti2020-07-062-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | This diff exposes parts of clock_gettime(2) and gettimeofday(2) to userland via libc eliberating processes from the need for a context switch everytime they want to count the passage of time. If a timecounter clock can be exposed to userland than it needs to set its tc_user member to a non-zero value. Tested with one or multiple counters per architecture. The timing data is shared through a pointer found in the new ELF auxiliary vector AUX_openbsd_timekeep containing timehands information that is frequently updated by the kernel. Timing differences between the last kernel update and the current time are adjusted in userland by the tc_get_timecount() function inside the MD usertc.c file. This permits a much more responsive environment, quite visible in browsers, office programs and gaming (apparently one is are able to fly in Minecraft now). Tested by robert@, sthen@, naddy@, kmos@, phessler@, and many others! OK from at least kettenis@, cheloha@, naddy@, sthen@
* wire up kstat(4)dlg2020-07-061-2/+3
| | | | "looks right" deraadt@
* Remove no-op cn30xxgmx_reset_board().visa2020-07-043-12/+3
|
* Remove obsolete <machine/stdarg.h> header. Nowadays the varargvisa2020-06-301-3/+0
| | | | | | | | functionality is provided by <sys/stdarg.h> using compiler builtins. Tested in a ports bulk build on amd64 by naddy@ OK naddy@ mpi@
* Use <dev/clock_subr.h> in octrtc(4).visa2020-06-301-37/+58
| | | | OK pirofti@
* TNF rescinded clauses 3 & 4 in 2008 in NetBSD.jsg2020-06-271-8/+1
|
* Remove a dead store.visa2020-06-131-2/+1
|
* cpu_rnd_messybits() for mips64visa2020-06-051-10/+1
| | | | | | | Use CP0 Count as a basis. Also take noise from virtual memory activity by including BadVAddr. OK deraadt@ dlg@
* introduce "cpu_rnd_messybits" for use instead of nanotime in dev/rnd.c.dlg2020-05-311-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | rnd.c uses nanotime to get access to some bits that change quickly between events that it can mix into the entropy pool. it doesn't use nanotime to get a monotonically increasing set or ordered and accurate timestamps, it just wants something with bits that change. there's been discussions for years about letting rnd use a clock that's super fast to read, but not necessarily accurate, but it wasn't until recently that i figured out it wasn't interested in time at all, so things like keeping a fast clock coherent between cpu cores or correct according to ntp is unecessary. this means we can just let rnd read the cycle counters on cpus and things will be fine. cpus with cycle counters that vary in their speed and arent kept consistent between cores may even be desirable in this context. so this is the first step in converting rnd.c to reading cycle counter. it copies the nanotime backend to each arch, and they can replace it with something MD as a second step later on. djm@ suggested rnd_messybytes, but we landed on cpu_rnd_messybits. thanks to visa for his eyes. ok deraadt@ visa@ deraadt@ says he will help handle any MD fallout that occurs.
* dev/rndvar.h no longer has statistical interfaces (removed during variousderaadt2020-05-292-5/+2
| | | | | | conversion steps). it only contains kernel prototypes for 4 interfaces, all of which legitimately belong in sys/systm.h, which are already included by all enqueue_randomness() users.
* Retire <machine/varargs.h>.visa2020-05-271-3/+0
| | | | | | Nothing uses the header anymore. OK deraadt@ mpi@
* increment version numbers, due to recent RB_GOODSEED and fchmod +T changesderaadt2020-05-261-2/+2
|
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.