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* OPAL implements firmware calls that abstract communicating with the BMC overkettenis2021-01-232-1/+179
| | | | | | IPMI. Use these calls to add support for impi(4) on PowerNV systems. ok dlg@
* Enter power-saving mode on POWER9 (ISA v3)gkoehler2020-12-301-7/+94
| | | | | | | | | | | | | | | | | | | When opal(4) attaches, look in the device tree for a psscr value. In cpu_idle_cycle(), use this psscr value and the stop instruction to wait for the next interrupt. In mp kernels, cpu_unidle() now sends an interrupt. In "sysctl hw.sensors", the power and temperature sensors from opalsens(4) may show lower values. The cpu may exit stop at the system reset vector after losing user registers. If so, restore some registers. For now, ignore deeper stop states that would lose hypervisor registers. Our mp kernel uses only the first hardware thread of each core. Take the extra threads from the firmware and stop them forever; this may switch the core from SMT4 to single-thread mode and increase performance. partly by kettenis@, ok kettenis@
* Fix typo.kettenis2020-12-201-2/+2
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* The TCE table needs to be aligned on a boundary that is a multiple of itskettenis2020-12-201-2/+2
| | | | | size. Fixes booting on machines that have memory banks higher up in physical address space which needs a larger TCE table.
* Make sure we perform address translation to all elements of a DMA mapping.kettenis2020-11-151-2/+2
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* No need to print that we're the console device; wsdisplay(4) will do thatkettenis2020-10-301-4/+1
| | | | for us.
* Add a comment that explains why the major/minor of the device is setkettenis2020-10-301-8/+12
| | | | | unconditionally now that astfb(4) can be used as the console as well. Only print that we're the console if we actually are.
* Allow astfb(4) to become the console. At this point this is a "late" switchkettenis2020-10-301-2/+17
| | | | | and early kernel boot messages will appear on opalcons(4) until astfb(4) attaches.
* Implement a workaround for PCI devices that can't address the full 64-bitkettenis2020-10-251-7/+173
| | | | | PCI address space. Needed for radeondrm(4) and amdgpu(4) since Radeon GPUs only implement 36, 40 or 44 bits of address space.
* Prefer 32-bit MSI even if the hardware supports 64-bit MSI to workkettenis2020-10-241-5/+10
| | | | | around buggy Radeon cards that advertise 64-bit MSI but only implement 40 bits.
* Handle spurious interrupts.kettenis2020-10-101-2/+12
| | | | ok patrick@, deraadt@
* Add astfb(4), a driver for the framebuffer of the Aspeed BMC found onkettenis2020-10-011-0/+236
| | | | many POWER8 and POWER9 systems.
* correct size argument to free(9)jsg2020-10-011-2/+2
| | | | ok kettenis@
* Do the NULL -> cpu_info_primary conversion in the interrupt controllerkettenis2020-09-262-2/+8
| | | | | | drivers instead of the "midlayer". I had missed a couple of places in the midlayer and instead of fixing this in several places it is better to do it in the functions that get invoked in the end.
* Use an IPI, so hw.setperf affects all cores in the mp kernel.gkoehler2020-09-231-1/+7
| | | | | | | | | | Before, apm -A was speeding up only one core of my POWER9. Now, apm -A speeds up all cores, so my parallel builds are faster. I copy the idea from amd64 and i386: mp_setperf() sends an IPI to all cpus; the interrupt handler calls ul_setperf(). ok deraadt@ kettenis@
* Correctly pass the "struct cpu_info" pointer along when establishingkettenis2020-09-215-16/+15
| | | | | | | | interrupts. This fixes IPIs on machines with certain (newer?) OPAL firmware. It also allows implementing pci_intr_establish_cpu(9), which is needed for distributing interrupt handlers across CPUs. tested by gkoehler@
* Sprinkle some more eieio(); seems to avoid triggering the KASSERT(new > old).kettenis2020-09-031-3/+5
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* vfs_shutdown() is neccessary to ensure buffer cache drain before reexec()deraadt2020-09-021-1/+4
| | | | ok kettenis visa
* Implement address translation for bus_space_mmap(9).kettenis2020-09-011-1/+25
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* Store the device tree node in the pcitag_t.kettenis2020-09-011-3/+34
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* Reorganize the interrupt handler code to avoid a potential bogus KASSERT,kettenis2020-08-301-10/+12
| | | | | | handle the priority levels better and guarantee ordering of restoring the priority level after running an interrupt handler and checking for a new interrupt.
* Mark certain sections with debug information as "allocated" such that theykettenis2020-08-291-2/+14
| | | | | | | get picked up by ddb. This makes the "pp" and "show struct" commands that depends on CTF work. ok gkoehler@
* Declare hw_{prod,serial,uuid,vendor,ver} in <sys/systm.h>.visa2020-08-261-4/+1
| | | | OK deraadt@, mpi@
* Add xicp(4), a driver for the interrupt control presenter hardware foundkettenis2020-08-231-0/+283
| | | | on POWER8 CPUs.
* Add missing conversion from IPL to CPU priority.kettenis2020-08-231-2/+2
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* Attempt to support IODA2 bridges such as the one found on POWER8 chips.kettenis2020-08-231-3/+4
| | | | | These lack an "ibm,opal-available-m64-ranges" property, but it seems we can assume a 0-15 range. At least this is what Linux does.
* Don't grab the kernel lock for mpsafe interrupts.kettenis2020-07-221-3/+14
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* Implement IPIs.kettenis2020-07-222-26/+55
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* Attach secondary CPUs early like we now do on arm64.kettenis2020-07-211-4/+4
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* Add missing KERNEL_LOCK() and KERNEL_UNLOCK() calls.kettenis2020-07-211-1/+3
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* Load kernel as an initrd such that we have symbols in ddb.kettenis2020-07-181-4/+29
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* Pass boothowto and bootduid parameters to the booted kernel via thekettenis2020-07-181-2/+23
| | | | | | device tree. Make sure the RB_GOODRANDOM flag only gets set if we read a non-stale /etc/random.seed and we actually filled an .openbsd.randomdata segment.
* Add a pseudo-driver to "kexec" an OpenBSD/powerpc64 kernel. Heavilykettenis2020-07-162-0/+230
| | | | | based on the octboot driver that we use for octeon. To be used in the bootloader kernel.
* Reset firmware state upon reboot.kettenis2020-07-161-2/+16
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* Use SENSOR_ENERGY as the type of energy sensors.kettenis2020-07-151-2/+2
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* Make INTx interupts work.kettenis2020-07-141-2/+20
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* Add xics(4), a driver for the OPAL virtual ICS.kettenis2020-07-141-0/+81
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* Add hw.cpuspeed and hw.setperfgkoehler2020-07-101-1/+94
| | | | | | | | | Get the list of Pstates from OPAL, and use special registers to request a Pstate or check the current Pstate. The turbo Pstates are higher than the cpu's nominal speed, but the OCC's firmware should throttle down the cpu if it would overheat. ok kettenis@
* Add opalsens(4), a driver for sensors provided by the OPAL firmware.kettenis2020-07-072-1/+148
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* We need to set the bypass bit for "raw" DMA memory as well.kettenis2020-07-051-1/+23
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* Use IPL_TTY, at least for now, as the only consumer of OPAL interruptskettenis2020-07-021-2/+2
| | | | is opalcons(4).
* Use the right bus space tag when enabling MSI-X interrupts. Makes themkettenis2020-06-291-2/+2
| | | | actually work.
* Attach event counter.kettenis2020-06-291-1/+4
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* Accept input.kettenis2020-06-261-1/+59
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* Handle OPAL interrupts.kettenis2020-06-261-2/+116
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* Add support for level-triggered interrupts and unmask established interropts.kettenis2020-06-261-6/+25
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* avoid uninitialised pointer usejsg2020-06-261-2/+2
| | | | found with scan-build, ok kettenis@
* Add opalcons(4), a driver for the OPAL console.kettenis2020-06-222-1/+296
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* Fix calculation of the year.kettenis2020-06-191-2/+2
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* Remove debug code.kettenis2020-06-141-6/+1
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