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* - enable fenvmartynas2011-04-281-0/+3
| | | | - add nearbyint, nearbyintf and nearbyintl implemented using fenv
* On IP27 systems, fill the array of node hub widget numbers early, so that allmiod2011-04-171-1/+4
| | | | | | hubs are known during autoconf. Then, pick the most populated 2GB window as our DMA memory window. xbridge(4) can thus program the correct settings regardless of the order in which the xbow(4) attach.
* Rename a few xbow global variable names to make them less ambiguous.miod2011-04-051-1/+6
| | | | | | | | | Remember the hub widget number of each node, instead of only the master node. Use this in xbridge to compute the proper direct DMA map configuration register value (it needs to embed the hub widget number matching the physical address range). This should allow us to pick memory from a different node than the one we booted from, as the DMA window, if wanted.
* Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently.pirofti2011-03-236-24/+24
| | | | Discussed and okay drahn@. Okay deraadt@.
* Convert netisr to a normal soft interrupt instead of hanving MD codeclaudio2010-12-211-6/+1
| | | | | | for it. This makes the netisr a real C function which will help further development. No noticable performance change on i386 and amd64. With input from kettenis@ and miod@ additional OKs mikeb@ and henning@
* FPU control/status register defines, and upcoming userland functionmiod2010-09-171-0/+3
| | | | prototypes to allow control of the FPU c/sr FS field.
* move machine dependent GET_CPU_INFO(), getcurcpu(), setcurcpu() to arch/sgi. ok miod@syuu2010-09-112-3/+10
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* Move cache settings into hw_cpu_init_secondary() ok miod@syuu2010-09-091-1/+2
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* Implement bus_space_barrier() on sgi; on xbridge, this will also flushmiod2010-08-231-3/+13
| | | | the pci write buffers.
* Storeing current cpu_info address into LLAddr register, for curcpu().syuu2010-04-282-30/+4
| | | | | | | Instead of previous implementation, we won't use physical cpuid to fetch curcpu(). This requires to implement IP27/35 SMP. Implemented getcurcpu() and setcurcpu() for it, smp_malloc() renamed alloc_contiguous_pages() because now it only allocate by page. ok miod@
* Split the device_register() code responsible for boot path recognition intomiod2010-04-061-1/+5
| | | | | | | | | | | | two distinct sets of routines: one for the ARCBios-compatible path used on non-KL systems (such as O2 and Octane), and one for the KL system using dksc() paths. When trying to match a dksc() path, walk the KL configuration of the whole system until the dksc controller is found; since the controller numbers are not assigned sequentially and contiguously, the old code would not work on complex systems (such as when booting from controller #6 when #3 to #5 are unaffected).
* Add more KL grovelling routines: one routine to enumerate on all nodes,miod2010-04-061-2/+6
| | | | | | | | | | and routines to turn a KL console and a KL component structs, respectively, into struct sgi_device_location for further device identification. XXX Due to the way PCI devices are numbered on PIC buses, this code is tainted XXX by knowledge about PIC widgets, to compensate. I have considered changing XXX xbridge(4) to have our PCI device numbering match KL on PIC-connected XXX devices, but I expect this to be even uglier. This is not settled yet.
* Introduce struct sgi_device_location to carry enough information to uniquelymiod2010-04-061-1/+25
| | | | | identify a given device by its physical connection, and add a lazy compare routine. This will be used shortly.
* Fix bus_space_{read,write}_raw_region_# operation.miod2010-04-041-3/+3
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* Update KL structure definitions to match IP35 use of previously unused fields.miod2010-03-211-38/+96
| | | | No functional change yet.
* On Origin-like systems, get glass console information (if any) from themiod2010-03-071-1/+2
| | | | | | fake ARCBios component structures associated to the KL configuration. The ARCBios data tells us if the device is the output console, and the KL component data tells us its node and widget numbers.
* Define IPL_SCHED as IPL_CLOCK, not IPL_HIGH.miod2010-01-181-3/+4
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* Move cache information from global variables to per-cpu_info fields; thismiod2010-01-092-20/+22
| | | | | | allows processors with different cache sizes to be used. Cache management routines now take a struct cpu_info * as first parameter.
* Define struct cpu_hwinfo, to hold hardware specific information about eachmiod2010-01-092-17/+4
| | | | | | | | | | | | processor (instead of sys_config.cpu[]), and pass it in the attach_args when attaching cpu devices. This allows per-cpu information to be gathered late in the bootstrap process, and not be limited by an arbitrary MAX_CPUS limit; this will suit IP27 and IP35 systems better. While there, use this information to make sure delay() uses the speed information from the cpu it is invoked on.
* Fix compile error caused from previous commitsyuu2009-12-281-1/+2
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* MP-safe pmap implemented, enable IPI in interrupt handler to avoid deadlock.syuu2009-12-282-5/+10
| | | | ok miod@
* Pass both the virtual address and the physical address of the memory rangemiod2009-12-253-19/+85
| | | | | | | | | | when invoking the cache functions. The physical address is needed when operating on physically-indexed caches, such as the L2 cache on Loongson processors. Preprocessor abuse makes sure that the physical address computation gets compiled out when running on a kernel compiled for virtually-indexed caches only, such as the sgi kernel.
* Switch page size from 4KB to 16KB on R10k kernels without R5k supportmiod2009-12-121-1/+7
| | | | (i.e. IP27 and IP30 sgi kernels).
* Unconditionnaly move kernel virtual memory space to XKSEG, now that previousmiod2009-12-081-19/+1
| | | | context.S fixes allows these settings to work for kernels linked in CKSEG0.
* Support for 16KB page size kernels; page size is now set in <machine/param.h>miod2009-12-071-1/+3
| | | | | | | | | | rather than <mips64/param.h>. For now, kernels are kept at 4KB to give people some time to build 16KB compatible binaries; this will change before the end of this release cycle. Use of 16KB page size kernels yields a 18% speedup (which, offset by the 1.6% slowdown caused by the pmap changes, yields a 16.6% overall speedup).
* IPL_IPI priority raised to IPL_IPI > IPL_HIGH for handling TLB shootdown.syuu2009-12-021-3/+3
| | | | ok miod@
* Use the new Elfxx_Phdr check hook to prevent loading a kernel not compiledmiod2009-11-301-2/+4
| | | | | for the platform we are running on (i.e. trying to boot e.g. bsd.IP32 on an IP27 machine).
* Now IPI can interrupt to clock interrupt handler.syuu2009-11-261-2/+3
| | | | | It prevents deadlock with TLB shootdown and clock interrupt. ok miod@
* IP30 IPI implementation.syuu2009-11-252-5/+11
| | | | | Also few xheart modification for SMP. ok miod@
* Allow xbow_intr_establish() callers to provide optional storage for themiod2009-11-251-1/+3
| | | | struct intrhand, instead of having it malloc()'ed.
* grammar fixes in comments; from bradmiod2009-11-221-3/+3
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* Allow mips ports to override VM_{MIN,MAX}_KERNEL_ADDRESS, and provide themiod2009-11-221-1/+19
| | | | | | | address as a kernel variable for use by libkvm. On sgi IP27 and IP30 kernels, use XKSEG instead of CKSSEG; this will allow kernel KVM size to grow in the future if necessary.
* mplock, rw_cas implementedsyuu2009-11-211-0/+52
| | | | ok miod@
* More unused fields in struct sys_rec.miod2009-11-121-2/+1
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* In case an ioc(4) device has lost its NIC component, do not recognize itmiod2009-11-071-1/+2
| | | | | | | as the onboard ioc device, if one has already been found on this node. Also, on Origin 300, do not attempt to attach the PS/2 controller on the onboard ioc(4) since PS/2 ports are not wired.
* Change sgi system identification from a single system type list, to a smallermiod2009-11-071-1/+2
| | | | | | system type list (which really is the system family) and a subsystem type. No functional change yet.
* MP safe mutex.syuu2009-11-041-1/+2
| | | | ok miod@
* Support IP30 secondary cpu bootup. ok miod@syuu2009-10-302-2/+9
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* Rename struct confargs to struct mainbus_attach_args for consistency and alsomiod2009-10-261-4/+4
| | | | to prevent further abuse of it.
* Get rid of unused `frame' member of struct intrhand; only hardclock() needsmiod2009-10-261-2/+1
| | | | a frame and clock interrupt doesn't need a struct intrhand.
* Better crime/mace interrupt handling; interrupt information is no longermiod2009-10-261-7/+1
| | | | | | | | specified in the kernel configuration file, but is provided by macebus(4) as part of the child device attachment args, and provide both crime and mace interrupt bitmasks; this allows us to only really enable interrupt sources we care about, and to avoid invoking interrupt handler we don't need to for the few mace interrupts multiplexed at the crime level.
* Completely overhaul interrupt handling on sgi. Cpu state now only stores amiod2009-10-222-62/+49
| | | | | | | | | | | | | | | | logical IPL level, and per-platform (IP27/IP30/IP32) code will from the necessary hardware mask registers. This allows the use of more than one interrupt mask register. Also, the generic (platform independent) interrupt code shrinks a lot, and the actual interrupt handler chains and masking information is now per-platform private data. Interrupt dispatching is generated from a template; more routines will be added to the template to reduce platform-specific changes and share as much code as possible. Tested on IP27, IP30, IP32 and IP35.
* The recent cleanups make blatantly visible that the pending_int handlermiod2009-10-221-5/+5
| | | | | | | | does almost exactly what splx() is doing if ipending is zero, and triggers soft interrupts as well. So don't bother checking for ipending in splx, and always invoke pending_int, which gets renamed as splx_handler for consistency.
* unifdef -DIMASK_EXTERNAL to the mips code. Support for interrupt masking atmiod2009-10-221-30/+9
| | | | | | coprocessor 0 sr level might come back in the future if hardware support requires it, but at the moment it's getting in the way of larger changes. ``In the Attic, noone can hear you scream''
* Replace intrmask_t with uint32_t. This types only describes interrupt masksmiod2009-10-221-13/+8
| | | | | | in the coprocessor 0 status register (coupled with ICR on rm7k/rm9k), and may be completely alien to real hardware interrupt masks, so don't make things unnecessary confusing.
* Replace IP32 hw_setintrmask() .S routine with a two line C routine.miod2009-10-211-2/+1
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* Get serial console speed from prom, and use it instead of hardcoding 9600 bps,miod2009-10-162-3/+4
| | | | | | on all systems but O2 (to catch up soon). Also use the IOC4 MCR register to figure out the IOC4 clock, instead of checking the widget control register, to be consistent with iof(4).
* Add some comments to explain why the DMA32 physseg is really 2**31 bytesmiod2009-10-141-3/+14
| | | | long. Prompted by deraadt@ long ago.
* Recognize more brick types and probe fooX bricks in the same order asmiod2009-10-081-1/+6
| | | | | foo bricks (they differ by having PCI-X bridges instead of PCI bridges but are otherwise built the same)
* ipending, cpl moved into cpu_infosyuu2009-10-071-4/+1
| | | | OK miod@
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