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2020-07-18Userland timecounter implementation for octeonvisa1-2/+2
OK naddy@; no objections from kettenis@
2020-07-06Add support for timeconting in userland.pirofti1-0/+23
This diff exposes parts of clock_gettime(2) and gettimeofday(2) to userland via libc eliberating processes from the need for a context switch everytime they want to count the passage of time. If a timecounter clock can be exposed to userland than it needs to set its tc_user member to a non-zero value. Tested with one or multiple counters per architecture. The timing data is shared through a pointer found in the new ELF auxiliary vector AUX_openbsd_timekeep containing timehands information that is frequently updated by the kernel. Timing differences between the last kernel update and the current time are adjusted in userland by the tc_get_timecount() function inside the MD usertc.c file. This permits a much more responsive environment, quite visible in browsers, office programs and gaming (apparently one is are able to fly in Minecraft now). Tested by robert@, sthen@, naddy@, kmos@, phessler@, and many others! OK from at least kettenis@, cheloha@, naddy@, sthen@
2020-06-30Remove obsolete <machine/stdarg.h> header. Nowadays the varargvisa1-5/+0
functionality is provided by <sys/stdarg.h> using compiler builtins. Tested in a ports bulk build on amd64 by naddy@ OK naddy@ mpi@
2020-05-27Retire <machine/varargs.h>.visa1-5/+0
Nothing uses the header anymore. OK deraadt@ mpi@
2020-04-14Fix some of the more esoteric bus_space functions. Thekettenis1-7/+8
bus_space_read_region_n, bus_space_write_region_n and bus_space_set_region_n functions were all broken. Same fix as arm64; Thanks to patrick@ for noting that mips64 had the same code. ok visa@
2019-09-05Implement splassert() on mips64.visa1-1/+17
2019-09-05Adjust interrupt priority levels on mips64 so that prioritiesvisa1-23/+20
of soft interrupts are lower than priorities of hard interrupts. This allows the delivery of hard interrupts while soft interrupts are masked.
2018-08-20Remove unused spllock().visa1-2/+1
OK deraadt@ mpi@
2018-01-22Include <sys/mutex.h> instead of <machine/mutex.h>mpi1-2/+2
required by upcoming MI mutex change.
2017-08-12Add a dummy (for now) <machine/reloc.h> for mips64 to fix build.visa1-0/+5
OK guenther@
2017-07-30Define MAXCPUS per mips64 port.visa1-1/+2
2017-06-11Define register_splx_handler() in one place.visa1-13/+2
2017-05-11The device_to_pa routine really isn't needed. We always have physicalvisa1-4/+4
addresses. While there, pave the way for BUS_DMA_64BIT (not working yet). Diff from miod@; OK dlg@
2017-05-08add a BUS_DMA_64BIT flag to bus_dma on all our archs.dlg1-1/+2
this is so drivers can advertise that they can handle 64 dma addresses to the platform. it may choose to handle dmamaps differently based on this flag. tweaks and ok tom@ ok kettenis@
2017-02-11Let MP-safe interrupt handlers run without the kernel lock on sgi.visa1-2/+3
OK miod@
2016-03-06Rename mips64's trap_frame into trapframe.mpi1-3/+3
For coherency with other archs and in order to use it in MI code. ok visa@, tobiasu@
2015-12-25Add IPI logic. Assign two additional interrupts for inter-processorvisa1-1/+3
signalling as a workaround to a limitation in the hub interrupt code, to allow four CPUs per node. At the moment, multi-node setups are not supported.
2015-12-25Make interrupt masking MP-aware. Linux IP27 and IP35 ports served as avisa1-1/+2
substitute for hardware documentation.
2015-12-25Use the ErrorEPC register for curcpu() on Origin, for now.visa1-4/+11
2015-09-30Use consistant whitespace/comments for #define'ing LABELSECTOR,krw1-4/+4
LABELOFFSET and MAXPARTITIONS. Easier on the eye when scanning through all these files. No functional change.
2015-09-13intr_barrier(9) for loongson, octeon and sgi.kettenis1-1/+3
2015-09-09The mplock implementations on MP-enabled mips64 platforms, octeon andvisa1-51/+2
sgi, are identical. Put one implementation in mips64 and drop the platform-specific copies, to remove duplicated code. ok miod@
2015-07-17Remove {LOAD,COUNT}_TEXTA from libsa loadfile, it only made sense for a.outmiod1-3/+3
kernels and we no longer have any.
2015-07-08unify the mutex implementations on all the mips64 platforms.dlg2-73/+5
this basically copies the sgi implementation to mips64 and removes it from the rest. this way they get an optimised UP mutex implementation and correct asserts on all platforms. ok miod@ jmatthew@
2015-04-21rework sgi mutexes to use the owner pointer as the lock.dlg1-6/+5
this is like src/sys/arch/alpha/alpha/mutex.c r1.14. this changes sgi mutexes so they record which cpu owns the lock rather than just if the lock is held or not. the diagnostics compare the owner to the current cpus curcpu() address so they can actually tell if the current cpu holds the lock instead of whether any cpu holds the lock. instead of using custom asm to implement a cas this uses atomic_cas_ptr. while im here i also shuffled the code. on MULTIPROCESSOR systems instead of duplicating code between mtx_enter and mtx_enter_try, mtx_enter simply loops on mtx_enter_try until it succeeds. this also provides an alternative implementation of mutexes on !MULTIPROCESSOR systems that avoids interlocking opcodes. mutexes wont contend on UP boxes, theyre basically wrappers around spls. we can just do the splraise, stash the owner as a guard value for DIAGNOSTIC and return. similarly, mtx_enter_try on UP will never fail, so we can just call mtx_enter and return 1. tested by and ok miod@
2014-07-13Remove stale comment which used to explain why we had a special 31-bit freelistmiod1-12/+1
for DMA, back when this was applicable.
2014-03-10Support BUS_DMA_NOCACHE in bus_dma(9). Memory allocations done withmiod1-15/+16
BUS_DMA_NOCACHE (or BUS_DMA_COHERENT if the platform does not have coherent caches) will use PMAP_NOCACHE when invoking pmap_enter(), to avoid creating cached mappings, and then evicting them from the cache.
2014-03-09Rework the per-cpu cache information. Use a common struct to store the linemiod1-2/+1
size, the number of sets, and the total size (and the set size, for convenience) per cache (I$, D$, L2, L3). This allows cpu.c to print the number of ways (sets) of L2 and L3 caches from the cache information, rather than hardcoding this from the processor type.
2014-02-10To prevent lock ordering problems with the kernel lock, we need to make surekettenis1-3/+18
we block all interrupts that can grab the kernel lock. The simplest way to achieve this is to make sure mutexes always raise the ipl to the highest level that has interrupts that grab the kernel lock. This will allow us to have "mpsafe" interrupt handlers at lower priority levels. No change for non-MULTIPROCESSOR kernels. ok miod@
2013-10-17Remove support for a.out and ecoff. We only do elf now.deraadt1-5/+0
ok miod
2013-06-01add missing license (PD) blockjasper2-4/+4
ok guenther@
2013-05-17Add a dummy IPL_MPSAFE definition.kettenis1-1/+4
ok miod@, mikeb@
2013-04-21Unify the zs tty driver.sebastia1-2/+2
Most of the hard work by mpi@, who provided the initial diff. Fixes for sparc from myself. Tested on sgi and sparc myself. Compiles and detects zstty on my powerbook, compile tested on sparc64 by me. Real testing with zs device on sparc64 by miod@ who also gave a lot of help and feedback. ok miod@, mpi@
2013-03-28Add __strong_alias macros for all architectures to be able to aliasmartynas1-6/+1
another symbol without weak attribute. To be used in libc and libm soon. Agreed by kettenis@, guenther@, matthew@.
2013-03-23refactor sys/param.h and machine/param.h. A lot of #ifdef _KERNEL is addedderaadt1-11/+6
to keep definitions our of user space. The MD files now follow a consistant order -- all namespace intrusion is at the tail can be cleaned up independently. locore, bootblocks, and libkvm still see enough visibility to build. Checked on 90% of platforms...
2012-06-26create new machine/_float.h which is namespace clean. create a newderaadt3-8/+3
MI float.h which pulls in and defines the values that are needed from there, and repair sys/limits.h so that it defines the values it needs as well (depending on POSIX version, XPG version, etc). guenther has a more exact selection of that coming for limits.h. this also fixes a few mistakes for the vax. reviewed by kettenis and guenther.
2012-06-24Add cache operation functions pointers to struct cpu_info; the variousmiod2-26/+3
cache lines and sizes are already there, after all. The ConfigCache cache routine is responsible for filling these function pointers; cache routine invocation macros are updated to use the cpu_info fields, but may still be overriden in <machine/cpu.h> on platforms where only one set of cache routines is used.
2012-06-17Using the LLAddr register to store our curcpu() pointer on R10k SMP kernelsmiod1-6/+28
was a nice trick, but this register is only 32-bit wide and will be sign-extended, which requires all cpu_info structs to be allocated within 2GB physical - something which may not be possible on some configurations. This diff changes IP30.MP kernels to no longer use LLAddr to store curcpu, but use unused fields of the MPConf structure in low memory, indexed with the physical processor id, which can be obtained from the Heart PRID register.
2012-05-29Make it possible to disable the Sync-on-Green signal by setting themikeb1-1/+2
ARCBios environment variable OSLoadOptions to "nosog". Now everyone can enjoy running O2 without an SGI monitor and don't turn vegetarian afterwards. All the essential bits come from NetBSD's crmfb driver except they've chosen to use a "SyncOnGreen" variable not saved by the ARCS. Pointers and corrections from and ok miod, jsing
2012-05-27Proper support for the so-called `fast mode' of the Indigo2 ECC memorymiod1-1/+4
controller. In this mode, access to physical memory are not allowed to bypass the cache, and this allows the memory subsystem to run faster. Of course, some device drivers will require uncached memory access (e.g. for proper HPC DMA descriptor operation). New ip22-specific functions to switch between `fast mode' and `slow mode' are introduced. hpc(4) now provides read and write routines to fetch a dma descriptor from uncached memory into a local copy, and update it from said modified copy. On systems without the ECC MC, these will do nothing and operation will continue to access the uncached memory directly. On systems with the ECC MC, they will perform a copy, and the writeback will be done in slow mode. bus_dmamem_map() requests for DMA memory with BUS_DMA_COHERENT set in flags, which would return uncached memory, will now always fail on systems with the ECC memory controller. Drivers which really need uncached memory, and are aware of this particular setup, will now pass BUS_DMA_COHERENT | BUS_DMA_BUS1, which will let the request succeed. sq(4) will use all of the above to work mostly unmodified on ECC MC systems in fast mode. Finally, fast mode is enabled after autoconf. Tested on IP22 and IP28.
2012-05-12It turns out that, when the IRIX header files mention CTR/DCD/DTR/RTS wiringmiod1-2/+2
is inverted on Indigo, this just means that Indigo does not use the same values as the later models. It does not mean that the Indigo is using wrong values, which is how I first read this. In reality, Indigo systems use the expected values of these signals being active low, while later designs use active high signals. So yes, some systems have inverted values - but the ones which need compensating are not those I thought. Change the logic to do TRT, but keep the device flags check, to be able to force the other behaviour if the kernel guesses wrongly. Tested on Indigo, Indy and Indigo 2.
2012-04-29I am not sure what the mess with the wiring of carrier lines on Indigo resolvesmiod1-1/+3
to, so make this controllable with device flags, and default to non-bogus wiring.
2012-04-21Rework the signature of the cache handling routines again. It makes more sensemiod2-11/+11
to pass both the virtual and physical addresses of the page to clean to SyncDCachePage, which is the only routine using `Index' operations on the data cache, which might be virtually indexed at some levels but physically indexed at others. On the other hand, it does not make any sense to pass a physical address to routines using `Hit' operations (and they were discarding them anyway). In addition to making things cleaner, this fixes sporadic userland misbehaviour (read: SIGSGEV) on RM7000 O2 systems.
2012-04-03Default DMA-reachable address constraints to the whole address space, andmiod1-1/+2
narrow these in the various ipXX_machdep.c. On IP22-like systems, narrow them to 28 bit physical addresses, but unpessimize this by extending this to 32 bit after autoconf, if no 28-bit limited hpc(4) device has been found. Since physical memory on these systems start at 128MB, this means that Indigo systems with more than 128MB memory will behave correctly (and so will Indy systems with E++ boards and more than 128MB memory).
2012-03-28Work in progress support for the SGI Indigo, Indigo 2 and Indy systemsmiod3-1/+191
(IP20, IP22, IP24) in 64-bit mode, adapated from NetBSD. Currently limited to headless operation, input and video drivers will get ported soon. Should work on all R4000, R4440 and R5000 based systems. L2 cache on R5000SC Indy not supported yet (coming soon), R4600 not supported yet either (coming soon as well). Tested to boot multiuser on: Indigo2 R4000SC, Indy R4000PC, Indy R4000SC, Indy R5000SC, Indigo2 R4400SC. There are still glitches in the Ethernet driver which are being looked at. Expansion support is limited to the GIO E++ board; GIO boards with PCI-GIO bridges not ported yet due to the lack of hardware, and this kind of driver does not port blindly. Most of this work comes from NetBSD, polishing and integration work, as well as putting as many ``R4x00 in 64-bit mode'' erratas as necessary, by yours truly. More work is coming, as well as trying to get some easy way to boot install kernels (as older PROM can only boot ECOFF binaries, which won't do for the kernel).
2012-03-25Move cache handling routines related definitions to a dedicated header file,miod1-6/+6
rather than abusing <machine/cpu.h>.
2012-03-19Change the page size computation logic to default to 16KB pages, and onlymiod1-4/+6
restrict to 4KB if the kernel is configured with R5000 or RM7000 family support. Allow the kernel configuration to override this if it knows better (e.g. an upcoming kernel configuration with support for R5000, but where physical memory on R5000 systems fits within the first 512MB).
2012-03-15No longer allow bus_space_barrier() to be a NULL pointer on a givenmiod1-5/+2
bus_space_tag on sgi, but rather always provide at least a dummy asm("sync") flavour. Saves a function pointer test at runtime.
2011-10-27Specify the TLS variant for each platform.guenther1-0/+3
2011-05-30Remove the freelist member from vm_physsegoga1-4/+1
The new world order of pmemrange makes this data completely redundant (being dealt with by the pmemrange constraints instead). Remove all code that messes with the freelist. While touching every caller of uvm_page_physload() anyway, add the flags argument to all callers (all but one is 0 and that one already used PHYSLOAD_DEVICE) and remove the macro magic to allow callers to continue without it. Should shrink the code a bit, as well. matthew@ pointed out some mistakes i'd made. ``freelist death, I like. Ok.' ariane@ `I agree with the general direction, go ahead and i'll fix any fallout shortly'' miod@ (68k 88k and vax i could not check would build)
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