summaryrefslogtreecommitdiffstats
path: root/sys/arch/sparc64/dev/msi.c (follow)
Commit message (Collapse)AuthorAgeFilesLines
* Implement pci_intr_establish_cpu() for pyro(4) and vpci(4) based sparc64jmatthew2020-06-231-10/+16
| | | | | | | | | | | | | | | | | systems. MSIs on these systems are delivered to event queues, which trigger interrupts when non-empty. The interrupt handler dequeues the MSIs and converts them into soft interrupts, which run on the same cpu as the event queue interrupt. To target pci device interrupts to different cpus, we set up an event queue per cpu in the system, or as many as we can, if there are fewer event queues available. For now, we don't have a way to feed this information back to intrmap, so instead we just map interrupts for cpus that don't have an event queue to another cpu that does have one. Tested on V215 (pyro), T5120, T4-1, S7-2 (vpci). dlg@ got the pyro side of it working for me. ok dlg@ kettenis@
* sizes for free(); ok semariederaadt2015-09-081-2/+2
|
* The hypervisor on a SPARC T5-2 needs stricter alignment of the MSI messagekettenis2014-11-241-2/+2
| | | | queue.
* add a size argument to free. will be used soon, but for now default to 0.tedu2014-07-121-2/+2
| | | | after discussions with beck deraadt kettenis.
* Split some generic MSI code out into its own file.kettenis2011-07-061-0/+86