wireguard-openbsd - WireGuard implementation for the OpenBSD kernel

	Commit message (Collapse)	Author	Age	Files	Lines
*	The i.MX SD/MMC host controller does not support zero-length DMA	patrick	2018-12-29	1	-3/+5
\| \| \| \| \| \| \| \| \|	descriptors, which are used to encode 64k transfers since it's a 16-bit value in the descriptor, which means that we only support a maximum segment size of 64k minus one. This fixes I/O errors on i.MX machines. ok kettenis@
*	Make imxesdhc(4) pass per-function cookies to the SD/MMC bus.	patrick	2018-08-09	1	-2/+11
\| \| \| \|	ok kettenis@
*	Give the FDT interrupt API a more generic naming by replacing the	patrick	2018-08-06	1	-2/+2
\| \| \| \| \| \|	arm_intr_* prefix with fdt_intr_*. ok kettenis@
*	Attach imxesdhc(4) to i.MX7D. Should attach to i.MX6SL as well.	kettenis	2018-06-10	1	-2/+4
\| \| \| \|	Needs the same quirk as i.MX6SX and i.MX8M.
*	imxesdhc(4) also supports High Speed mode for SD.	patrick	2018-06-04	1	-2/+2
\| \| \| \|	ok kettenis@
*	Clear the DMA select bits in case we use PIO instead of DMA. Some	patrick	2018-05-30	1	-2/+3
\| \| \| \| \| \| \| \| \|	SDHC controllers get confused if the ADMA bit is set even though we don't set the DMA enable flag. This can happen with the SDIO stack which uses PIO for 4 byte read/writes but DMA for larger transfers and thus switches from one mode to the other. ok kettenis@
*	For SDIO multi-blocks we must not use the AUTO CMD12 feature,	patrick	2018-05-25	1	-2/+4
\| \| \| \| \| \|	this is only for memory card read/writes. ok kettenis@
*	Set the assigned clock settings in imxesdhc(4), which leads to a frequency	patrick	2018-05-03	1	-1/+3
\| \| \| \|	bump to 400 MHz for the eMMC on i.MX8MQ.
*	The i.MX8M has the same quirk as the i.MX6SX, where the CAP1 register	patrick	2018-04-27	1	-2/+3
\| \| \| \|	spills into the CAP register.
*	Attach imxesdhc(4) to i.MX8M as well.	patrick	2018-03-30	1	-2/+3
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*	Move imxesdhc(4) to sys/dev/fdt.	patrick	2018-03-30	1	-0/+1210