| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Enable all clocks referenced by the imxesdhc(4) device tree node. Usually |   patrick | 2020-04-28 | 1 | -1/+2 |
| | | | | | | | | | | those are already on, since on those machines we mostly boot from SD/MMC and U-Boot prepares them for us. On machines with a WiFi on imxesdhc(4), U-Boot isn't necessarily configured to do so. Enabling the clocks is the right thing to do anyway. ok kettenis@ | ||||
| * | fix SDHC_DEBUG build, remove procname printf's |   ians | 2020-04-27 | 1 | -5/+4 |
| | | | | | ok kettenis@ | ||||
| * | Both i.MX8MM and i.MX8MQ use the same uSDHC as the i.MX7D, and | patrick | 2020-03-20 | 1 | -3/+3 |
| | | | | | | | | thus also use the same compatible. So replace the i.MX8MQ check with one for the i.MX7D to catch them all. ok kettenis@ | ||||
| * | Cleanup <sys/kthread.h> and <sys/proc.h> includes. |   mpi | 2020-02-18 | 1 | -2/+1 |
| | | | | | | | | Do not include <sys/kthread.h> where it is not needed and stop including <sys/proc.h> in it. ok visa@, anton@ | ||||
| * | Timeouts are all specified in multiple of `hz' so define them in term of | mpi | 2020-01-13 | 1 | -8/+9 |
| | | | | | | | seconds and use tsleep_nsec(9). ok patrick@ | ||||
| * | The i.MX SD/MMC host controller does not support zero-length DMA | patrick | 2018-12-29 | 1 | -3/+5 |
| | | | | | | | | | | descriptors, which are used to encode 64k transfers since it's a 16-bit value in the descriptor, which means that we only support a maximum segment size of 64k minus one. This fixes I/O errors on i.MX machines. ok kettenis@ | ||||
| * | Make imxesdhc(4) pass per-function cookies to the SD/MMC bus. | patrick | 2018-08-09 | 1 | -2/+11 |
| | | | | | ok kettenis@ | ||||
| * | Give the FDT interrupt API a more generic naming by replacing the | patrick | 2018-08-06 | 1 | -2/+2 |
| | | | | | | | arm_intr_* prefix with fdt_intr_*. ok kettenis@ | ||||
| * | Attach imxesdhc(4) to i.MX7D. Should attach to i.MX6SL as well. |   kettenis | 2018-06-10 | 1 | -2/+4 |
| | | | | | Needs the same quirk as i.MX6SX and i.MX8M. | ||||
| * | imxesdhc(4) also supports High Speed mode for SD. | patrick | 2018-06-04 | 1 | -2/+2 |
| | | | | | ok kettenis@ | ||||
| * | Clear the DMA select bits in case we use PIO instead of DMA. Some | patrick | 2018-05-30 | 1 | -2/+3 |
| | | | | | | | | | | SDHC controllers get confused if the ADMA bit is set even though we don't set the DMA enable flag. This can happen with the SDIO stack which uses PIO for 4 byte read/writes but DMA for larger transfers and thus switches from one mode to the other. ok kettenis@ | ||||
| * | For SDIO multi-blocks we must not use the AUTO CMD12 feature, | patrick | 2018-05-25 | 1 | -2/+4 |
| | | | | | | | this is only for memory card read/writes. ok kettenis@ | ||||
| * | Set the assigned clock settings in imxesdhc(4), which leads to a frequency | patrick | 2018-05-03 | 1 | -1/+3 |
| | | | | | bump to 400 MHz for the eMMC on i.MX8MQ. | ||||
| * | The i.MX8M has the same quirk as the i.MX6SX, where the CAP1 register | patrick | 2018-04-27 | 1 | -2/+3 |
| | | | | | spills into the CAP register. | ||||
| * | Attach imxesdhc(4) to i.MX8M as well. | patrick | 2018-03-30 | 1 | -2/+3 |
| | | |||||
| * | Move imxesdhc(4) to sys/dev/fdt. | patrick | 2018-03-30 | 1 | -0/+1210 |
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