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* Clean up nonexistent/unused properties handlingkn2021-04-011-12/+1
| | | | | | | | | | Never used since import and probably just ported over from NetBSD as-is; "design-capacity" does not exist in the device tree binding. "monitor-interval-ms" defaults to 250ms as per binding and could be used in the sensor_task_register() call, but our framework only supports whole seconds and there's no advantage over our current fixed poll interval of 5s. OK patrick
* Hardcode meaningful alert level, track apm's battery state betterkn2021-04-011-23/+7
| | | | | | | | | | | | | | | | | | | | The current code looks for the nonexistent "cellwise,alert-level" property and falls back to zero as threshold (like the original NetBSD code). It also updates the CONFIG register with that very threshold to let the hardware set a bit and thus alert us when it has been reached. Since our sensor framework is designed to poll every N seconds and this driver does not actually look at whether the hardware alerted, neither using a default threshold of zero nor updating the hardware with it makes sense. Remove the alert level code and simply map >50%, >25% and <=25% of remaining battery life to apm(4)'s "high", "low" and "critical" battery state respectively; this matches exactly what acpibat(4) does and provides more meaningful sensor readings without relying on nonexistent device tree bindings. Feedback OK patrick
* Flag sensors as invalid on bogus readskn2021-03-261-3/+7
| | | | | | | | | | | | | | | | | Follow-up to the previous commit: This driver continues to report stale hw.sensors values when reading them fails, which can easily be observed on a Pinebook Pro after plugging in the AC cable, causing the hw.sensors.cwfg0.raw0 (battery remaining minutes) value to jump considerably one or two times before stalling and becoming incoherent with the rest. Flag sensors invalid upfront in apm's fashion and mark them OK iff they yield valid values; this is what other drivers such as rktemp(4) do, but the consequence/intention of SENSOR_FINVALID is sysctl(8) and systat(8) skipping such sensors (until AC gets plugged off again). OK patrick
* Provide apm(4/arm64) with battery informationkn2021-03-251-1/+41
| | | | | | | | | | | | | | | | | | | | | | apm merely provides an all zero/unknown stub for those values, e.g. apm(8) output is useless. Hardware sensors however provide this information: hw.sensors.cwfg0.volt0=3.76 VDC (battery voltage) hw.sensors.cwfg0.raw0=259 (battery remaining minutes) hw.sensors.cwfg0.percent0=58.00% (battery percent) Make cwfg(4) copy those over using apm_setinfohook() for apm to show it: Battery state: high, 58% remaining, 259 minutes life estimate A/C adapter state: not known Performance adjustment mode: auto (408 MHz) In cwfg's update routine, to keep values coherent, always reset them to zero/unknown and only set those that came from a valid reading. Input OK jca
* Load MSI pages through bus_dma(9). Our interrupt controllers for MSIspatrick2021-03-221-4/+53
| | | | | | | | | | | | | | | | | | | | | | | | | typically pass the physical address, however retrieved, to our PCIe controller code. This physical address can in practise be directly given to the PCIe, but it is not a given that the CPU and the PCIe controller are able to use the same physical addresses. This is even more obvious with an smmu(4) inbetween, which can change the world view by introducing I/O virtual addresses. Hence for this it is indeed necessary to map those pages, which thanks to integration with bus_dma(9) works easily. For this we remember the PCI devices' DMA tag in the interrupt handle during the MSI map, so that we can use the smmu(4)-hooked DMA tag to load the physical address. While some systems might prefer to implement "trapping" pages for MSIs, to make sure devices cannot trigger other devices' interrupts, we only make sure the whole page is mapped. Having the IOMMU create a mapping for each MSI is a bit wasteful, but for now it's the simplest way to implement it. Discussed with and ok kettenis@
* Update device-tree bindingskn2021-03-221-6/+6
| | | | | | | | | | | | | | | | | Using the DTB from our dtb package this driver no longer attaches (on a Pinebook Pro)due to renamed bindings: https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/power/supply/cw2015_battery.yaml Thanks to kettenis and patrick for pointing this out. Follow upstream's rename and acccount for the monitor interval now being milliseconds not seconds anymore. This makes cwfg(4) export values under hw.sensors as expected when using /usr/local/share/dtb/arm64/rockchip/rk3399-pinebook-pro.dtb . Input patrick kettenis OK kettenis
* Advertise 30-bit color support.kettenis2021-03-131-2/+5
| | | | ok matthieu@, jsg@
* Make sure to skip attaching disabled I2C devices. This can happen onpatrick2021-03-115-10/+35
| | | | | | hardware which include a common parent block in their device trees and only enable the components that were actually implemented, as seen on e.g. the NanoPi R4S.
* Make sure to skip attaching disabled I2C devices. This can happen onpatrick2021-03-111-2/+7
| | | | | | | | hardware which include a common parent block in their device trees and only enable the components that were actually implemented, as seen on e.g. the NanoPi R4S. ok kettenis@
* Add support for 30-bit color modes.kettenis2021-03-091-2/+4
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* Add support for rk809 as seen on the Rock Pi N10 with the rk3399pro. Addkurt2021-03-081-57/+262
| | | | | | | support for multiple linear ranges for voltage regulators and use for all rkpmic ICs. ok kettenis@
* Transactions on the AXI bus contain a Stream ID. SMMUs filterpatrick2021-03-011-1/+15
| | | | | | | | | | | | | | | based on Stream IDs. On the Armada 8040 these Stream IDs can be configured in different registers. The PCIe controller has a register which maps root port, bus, dev and func number to the Stream ID. This should be set up by TF-A firmware, but on the 8040 the current images don't do this. For chips with more than one PCIe controller this register must be setup correctly depending on the implementation, but on the 8040 there only is one controller, so we can configure a fixed value to match what is defined in the device tree. This allows the SMMU to properly track the PCIe controller's transactions. ok kettenis@
* The ep-gpios property is optional on the Rockchip PCIe controller.patrick2021-03-011-11/+21
| | | | | | | | While there, enable the different voltage regulators and set the PHY's assigned clocks. This makes PCIe work on the NanoPi R4S. Tested by kurt@ on Rock Pi N10 and ROCKPro64 ok kurt@ kettenis@
* Issue call to IOMMU OFW API to collect an IOMMU-sprinkled DMA tag.patrick2021-02-281-1/+7
| | | | ok kettenis@
* Add some infrastructure in the PCI chipset tag for pci_probe_device_hook()patrick2021-02-254-4/+36
| | | | | | so that we can provide IOMMU-hooked bus DMA tags for each PCI device. ok kettenis@
* Disable double-data rate modes if 1.8V signalling is not possible.patrick2021-02-221-2/+4
| | | | ok kettenis@
* Slow mode is only relevant for legacy and high speed timings.patrick2021-02-221-3/+3
| | | | ok kettenis@
* Improve support for the variant found on the Apple M1 SoC.kettenis2021-02-222-64/+161
| | | | | | | This mostly adjust the interrupt masking and status support since this variant lacks the UINTM and UINTP registers. ok patrick@
* Add support for the UART found on the Apple M1 SoC.kettenis2021-02-162-10/+30
| | | | ok patrick@
* Introduce variables to deal with bit layout differences in the UFSTATkettenis2021-02-141-9/+26
| | | | | | | | | register. Use 32-bit reads and writes to access the URXH and UTXH registers. They're documented as 32-bit registers in the Exynos 4 and Exynos 5 User Manuals and accessing URXH with an 8-bit read triggers a fault on Apple's M1 SoC. ok patrick@
* Don't hardcode com(4)'s major number in exuart(4).patrick2021-02-111-5/+12
| | | | ok kettenis@
* arm_intr_establish_fdt() has long been renamed to fdt_intr_establish().patrick2021-02-053-8/+7
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* Fix CVS tag.patrick2021-02-051-1/+1
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* Fix whitespace.patrick2021-02-051-2/+2
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* Rename probe/attach functions to fit our regular naming scheme. Replacepatrick2021-02-051-13/+13
| | | | | | | | | &armv7_bs_tag with fdt_cons_bs_tag, which is our early console bus tag for both arm64 and armv7. On armv7, it points to &armv7_bs_tag. With this we can get rid of the armv7var.h include. Reduce a bit of diff to imxuart(4). ok kettenis@
* Move exuart(4) to sys/dev/fdt so it can be shared between arm64 and armv7.patrick2021-02-053-1/+1057
| | | | ok kettenis@
* Tedu unnecessary imxuartvar.h.patrick2021-02-042-21/+1
| | | | ok kettenis@
* handle #pinctrl-cells 2jsg2021-02-011-2/+7
| | | | | needed for >= linux 5.9 dtbs on bbb ok kettenis@
* Reprogram outbound windows to match the device tree. Necessary becausekettenis2021-01-201-3/+34
| | | | | | | the EDK2-based UEFI firmware sets it to its own hardcoded values. Makes device-tree mode work with newer versions of the Raspberry Pi firmware. ok patrick@
* Implement intx support.kettenis2021-01-191-19/+123
| | | | ok patrick@
* Handle pinctrl.kettenis2020-12-291-1/+4
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* Add more PWM pin descriptions.kettenis2020-12-291-1/+32
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* Add support for the PCIe controller found on Amlogic G12A/G12B/SM1 SoCs.kettenis2020-12-281-11/+119
| | | | ok patrick@
* Remove debug printf.kettenis2020-12-271-2/+1
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* Add PCIe support.kettenis2020-12-271-48/+68
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* Add PCIe power domain.kettenis2020-12-271-1/+14
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* Add PCIe clocks.kettenis2020-12-221-1/+5
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* Defer hardware initialization in order to give things like PCIe PHYskettenis2020-12-221-15/+31
| | | | | | a chance to attach. Needed for future support of PCIe on Amlogic SoCs. ok patrick@
* There's no need to include the OFW GPIO header.patrick2020-12-191-2/+1
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* Add support for the i.MX8MP PCIe clocks.patrick2020-12-192-1/+40
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* Add support for the i.MX8MP second ethernet. The Plus SoC not only has thepatrick2020-12-182-4/+98
| | | | | usual fec(4), but also a variant of dwge(4). Unfortunately it seems to be a newer version, which isn't compatible to the one currently in our tree.
* Emulate open drain GPIOs. This replaces the hack added in the last commit.kettenis2020-12-181-31/+22
| | | | ok patrick@
* Make large read and write transactions work.kettenis2020-12-181-39/+59
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* Add glue for the USB3 controller on the i.MX8MP SoC. NXP had this glue forpatrick2020-12-182-1/+80
| | | | | | | | | | | the i.MX8MQ as well, but while upstreaming they were told to shove it. Now for the i.MX8MP this glue is making a comeback. Apparently there's some divergence in low power handling to the regular DWC3 IP with special IRQs. Now the question remains if this driver will be obsolete soon again, or if this time it's here to stay. The fun part is that while this driver was written independent from the previous version, the diff is basically zero. ok kettenis@
* Add code to initialize the USB 3 PHY on i.MX8MP.patrick2020-12-181-2/+65
| | | | ok kettenis@
* Add support for the i.MX8MP USB clocks.patrick2020-12-182-2/+88
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* Attach imxgpc(4) to i.MX8MP as well.patrick2020-12-181-1/+3
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* Only enable the USB 3.0 port and PHY if it is enabled on a board.kettenis2020-12-171-5/+7
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* Reset pin 3 of the GPIOAO bank to input mode to work around a hardwarekettenis2020-12-171-2/+31
| | | | bug in the Odroid C4/HC4 boards.
* Match on "amlogic,meson-g12a-dwmac" which is used by newer Linux mainlinekettenis2020-12-171-1/+2
| | | | device trees.
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